622 lines
21 KiB
C
622 lines
21 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_wm8960.h"
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#include "fsl_common.h"
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/*******************************************************************************
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* Definitations
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******************************************************************************/
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*
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* wm8960 register cache
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* We can't read the WM8960 register space when we are
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* using 2 wire for device control, so we cache them instead.
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*/
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static const uint16_t wm8960_reg[WM8960_CACHEREGNUM] = {
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0x0097, 0x0097, 0x0000, 0x0000, 0x0000, 0x0008, 0x0000, 0x000a, 0x01c0, 0x0000, 0x00ff, 0x00ff, 0x0000, 0x0000,
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0x0000, 0x0000, 0x0000, 0x007b, 0x0100, 0x0032, 0x0000, 0x00c3, 0x00c3, 0x01c0, 0x0000, 0x0000, 0x0000, 0x0000,
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0x0000, 0x0000, 0x0000, 0x0000, 0x0100, 0x0100, 0x0050, 0x0050, 0x0050, 0x0050, 0x0000, 0x0000, 0x0000, 0x0000,
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0x0040, 0x0000, 0x0000, 0x0050, 0x0050, 0x0000, 0x0002, 0x0037, 0x004d, 0x0080, 0x0008, 0x0031, 0x0026, 0x00e9,
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};
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static uint16_t reg_cache[WM8960_CACHEREGNUM];
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/*******************************************************************************
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* Code
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******************************************************************************/
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void WM8960_Init(wm8960_handle_t *handle, wm8960_config_t *config)
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{
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uint32_t i = 4000000;
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memcpy(reg_cache, wm8960_reg, sizeof(wm8960_reg));
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/* Set WM8960 I2C address */
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handle->xfer.slaveAddress = WM8960_I2C_ADDR;
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/* NULL pointer means default setting. */
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if (config == NULL)
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{
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/*
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* Reset all registers
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*/
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WM8960_WriteReg(handle, WM8960_RESET, 0x00);
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WM8960_WriteReg(handle, WM8960_IFACE2, 0x40);
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/*
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* VMID=50K, Enable VREF, AINL, AINR, ADCL and ADCR
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* I2S_IN (bit 0), I2S_OUT (bit 1), DAP (bit 4), DAC (bit 5), ADC (bit 6) are powered on
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*/
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WM8960_WriteReg(handle, WM8960_POWER1, 0xCA);
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/*
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* Enable DACL, DACR, LOUT1, ROUT1, PLL down
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*/
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WM8960_WriteReg(handle, WM8960_POWER2, 0x1E0);
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/*
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* Enable left and right channel input PGA, left and right output mixer
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*/
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WM8960_WriteReg(handle, WM8960_POWER3, 0xC);
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/* Configure SYS_FS clock to 44.1kHz, MCLK_FREQ to 256*Fs, SYSCLK derived from MCLK input */
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WM8960_WriteReg(handle, WM8960_CLOCK1, 0x00);
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/*
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* Audio data length = 32bit, Left justified data format
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*/
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WM8960_WriteReg(handle, WM8960_IFACE1, 0x0D);
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/*
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* LMICBOOST = 0dB, Connect left and right PGA to left and right Input Boost Mixer
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*/
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WM8960_WriteReg(handle, WM8960_LINPATH, 0x18);
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WM8960_WriteReg(handle, WM8960_RINPATH, 0x18);
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/*
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* Left and right input boost, LIN3BOOST and RIN3BOOST = 0dB
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*/
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WM8960_WriteReg(handle, WM8960_INBMIX1, 0x70);
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WM8960_WriteReg(handle, WM8960_INBMIX2, 0x70);
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/*
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* Left DAC and LINPUT3 to left output mixer, LINPUT3 left output mixer volume = 0dB
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*/
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WM8960_WriteReg(handle, WM8960_LOUTMIX, 0x100);
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/*
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* Right DAC and RINPUT3 to right output mixer, RINPUT3 right output mixer volume = 0dB
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*/
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WM8960_WriteReg(handle, WM8960_ROUTMIX, 0x100);
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WM8960_WriteReg(handle, WM8960_BYPASS1, 0x0);
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WM8960_WriteReg(handle, WM8960_BYPASS2, 0x0);
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WM8960_WriteReg(handle, WM8960_MONOMIX1, 0x00);
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WM8960_WriteReg(handle, WM8960_MONOMIX2, 0x00);
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}
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else
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{
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WM8960_SetDataRoute(handle, config->route);
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WM8960_SetProtocol(handle, config->bus);
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WM8960_SetMasterSlave(handle, config->master_slave);
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}
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WM8960_WriteReg(handle, WM8960_ADDCTL1, 0x0C4);
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WM8960_WriteReg(handle, WM8960_ADDCTL4, 0x40);
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/*
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* ADC volume, 0dB
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*/
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WM8960_WriteReg(handle, WM8960_LADC, 0x1F3);
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WM8960_WriteReg(handle, WM8960_RADC, 0x1F3);
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/*
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* Digital DAC volume, 0dB
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*/
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WM8960_WriteReg(handle, WM8960_LDAC, 0x1E0);
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WM8960_WriteReg(handle, WM8960_RDAC, 0x1E0);
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/*
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* Headphone volume, LOUT1 and ROUT1, 0dB
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*/
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WM8960_WriteReg(handle, WM8960_LOUT1, 0x16F);
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WM8960_WriteReg(handle, WM8960_ROUT1, 0x16F);
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/* Delay for some while */
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while (i)
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{
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__ASM("nop");
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i--;
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}
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/* Unmute DAC. */
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WM8960_WriteReg(handle, WM8960_DACCTL1, 0x0000);
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}
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void WM8960_Deinit(wm8960_handle_t *handle)
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{
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WM8960_SetModule(handle, kWM8960_ModuleADC, false);
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WM8960_SetModule(handle, kWM8960_ModuleDAC, false);
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WM8960_SetModule(handle, kWM8960_ModuleVREF, false);
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WM8960_SetModule(handle, kWM8960_ModuleLineIn, false);
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WM8960_SetModule(handle, kWM8960_ModuleLineOut, false);
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WM8960_SetModule(handle, kWM8960_ModuleSpeaker, false);
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}
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void WM8960_SetMasterSlave(wm8960_handle_t *handle, bool master)
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{
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if (master == 1)
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{
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WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_MS_MASK, WM8960_IFACE1_MS(WM8960_IFACE1_MASTER));
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}
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else
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{
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WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_MS_MASK, WM8960_IFACE1_MS(WM8960_IFACE1_SLAVE));
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}
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}
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status_t WM8960_SetModule(wm8960_handle_t *handle, wm8960_module_t module, bool isEnabled)
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{
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status_t ret = kStatus_Success;
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switch (module)
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{
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case kWM8960_ModuleADC:
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WM8960_ModifyReg(handle, WM8960_POWER1, WM8960_POWER1_ADCL_MASK,
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((uint16_t)isEnabled << WM8960_POWER1_ADCL_SHIFT));
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WM8960_ModifyReg(handle, WM8960_POWER1, WM8960_POWER1_ADCR_MASK,
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((uint16_t)isEnabled << WM8960_POWER1_ADCR_SHIFT));
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break;
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case kWM8960_ModuleDAC:
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WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_DACL_MASK,
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((uint16_t)isEnabled << WM8960_POWER2_DACL_SHIFT));
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WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_DACR_MASK,
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((uint16_t)isEnabled << WM8960_POWER2_DACR_SHIFT));
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break;
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case kWM8960_ModuleVREF:
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WM8960_ModifyReg(handle, WM8960_POWER1, WM8960_POWER1_VREF_MASK,
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((uint16_t)isEnabled << WM8960_POWER1_VREF_SHIFT));
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break;
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case kWM8960_ModuleLineIn:
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WM8960_ModifyReg(handle, WM8960_POWER1, WM8960_POWER1_AINL_MASK,
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((uint16_t)isEnabled << WM8960_POWER1_AINL_SHIFT));
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WM8960_ModifyReg(handle, WM8960_POWER1, WM8960_POWER1_AINR_MASK,
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((uint16_t)isEnabled << WM8960_POWER1_AINR_SHIFT));
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break;
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case kWM8960_ModuleLineOut:
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WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_LOUT1_MASK,
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((uint16_t)isEnabled << WM8960_POWER2_LOUT1_SHIFT));
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WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_ROUT1_MASK,
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((uint16_t)isEnabled << WM8960_POWER2_ROUT1_SHIFT));
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break;
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case kWM8960_ModuleSpeaker:
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WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_SPKL_MASK,
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((uint16_t)isEnabled << WM8960_POWER2_SPKL_SHIFT));
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WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_SPKR_MASK,
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((uint16_t)isEnabled << WM8960_POWER2_SPKR_SHIFT));
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WM8960_WriteReg(handle, WM8960_CLASSD1, 0xF7);
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break;
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default:
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ret = kStatus_InvalidArgument;
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break;
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}
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return ret;
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}
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status_t WM8960_SetDataRoute(wm8960_handle_t *handle, wm8960_route_t route)
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{
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status_t ret = kStatus_Success;
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switch (route)
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{
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case kWM8960_RouteBypass:
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/* Bypass means from line-in to HP*/
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/*
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* Left LINPUT3 to left output mixer, LINPUT3 left output mixer volume = 0dB
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*/
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WM8960_WriteReg(handle, WM8960_LOUTMIX, 0x80);
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/*
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* Right RINPUT3 to right output mixer, RINPUT3 right output mixer volume = 0dB
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*/
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WM8960_WriteReg(handle, WM8960_ROUTMIX, 0x80);
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break;
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case kWM8960_RoutePlayback:
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/* Data route I2S_IN-> DAC-> HP */
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/*
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* Left DAC to left output mixer, LINPUT3 left output mixer volume = 0dB
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*/
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WM8960_WriteReg(handle, WM8960_LOUTMIX, 0x100);
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/*
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* Right DAC to right output mixer, RINPUT3 right output mixer volume = 0dB
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*/
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WM8960_WriteReg(handle, WM8960_ROUTMIX, 0x100);
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break;
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case kWM8960_RoutePlaybackandRecord:
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/* I2S IN->DAC->HP LINE_IN->ADC->I2S_OUT */
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/*
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* Left and right input boost, LIN3BOOST and RIN3BOOST = 0dB
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*/
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WM8960_WriteReg(handle, WM8960_INBMIX1, 0x50);
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WM8960_WriteReg(handle, WM8960_INBMIX2, 0x50);
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/*
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* Left DAC to left output mixer, LINPUT3 left output mixer volume = 0dB
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*/
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WM8960_WriteReg(handle, WM8960_LOUTMIX, 0x100);
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/*
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* Right DAC to right output mixer, RINPUT3 right output mixer volume = 0dB
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*/
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WM8960_WriteReg(handle, WM8960_ROUTMIX, 0x100);
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break;
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case kWM8960_RoutePlaybackwithDAP:
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/* I2S_IN->DAP->DAC->HP */
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break;
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case kWM8960_RoutePlaybackwithDAPandRecord:
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/* I2S_IN->DAP->DAC->HP, LINE_IN->ADC->I2S_OUT */
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break;
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case kWM8960_RouteRecord:
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/* LINE_IN->ADC->I2S_OUT */
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/*
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* Left and right input boost, LIN3BOOST and RIN3BOOST = 0dB
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*/
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WM8960_WriteReg(handle, WM8960_INBMIX1, 0x50);
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WM8960_WriteReg(handle, WM8960_INBMIX2, 0x50);
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break;
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default:
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ret = kStatus_InvalidArgument;
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break;
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}
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return ret;
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}
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status_t WM8960_SetProtocol(wm8960_handle_t *handle, wm8960_protocol_t protocol)
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{
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status_t ret = kStatus_Success;
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switch (protocol)
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{
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case kWM8960_BusI2S:
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WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK,
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WM8960_IFACE1_FORMAT(WM8960_IFACE1_FORMAT_I2S));
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break;
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case kWM8960_BusLeftJustified:
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WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK,
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WM8960_IFACE1_FORMAT(WM8960_IFACE1_FORMAT_LJ));
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break;
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case kWM8960_BusRightJustified:
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WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK,
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WM8960_IFACE1_FORMAT(WM8960_IFACE1_FORMAT_RJ));
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break;
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case kWM8960_BusPCMA:
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WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK,
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WM8960_IFACE1_FORMAT(WM8960_IFACE1_FORMAT_DSP));
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WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_LRP_MASK, WM8960_IFACE1_LRP(WM8960_IFACE1_DSP_MODEA));
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break;
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case kWM8960_BusPCMB:
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WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK,
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WM8960_IFACE1_FORMAT(WM8960_IFACE1_FORMAT_DSP));
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WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_LRP_MASK, WM8960_IFACE1_LRP(WM8960_IFACE1_DSP_MODEB));
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break;
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default:
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ret = kStatus_InvalidArgument;
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break;
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}
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WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL(WM8960_IFACE1_WL_32BITS));
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return ret;
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}
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status_t WM8960_SetVolume(wm8960_handle_t *handle, wm8960_module_t module, uint32_t volume)
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{
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uint16_t vol = 0;
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status_t ret = kStatus_Success;
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switch (module)
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{
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case kWM8960_ModuleADC:
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vol = 0x100 | volume;
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ret = WM8960_WriteReg(handle, WM8960_LADC, vol);
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ret = WM8960_WriteReg(handle, WM8960_RADC, vol);
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break;
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case kWM8960_ModuleDAC:
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vol = 0x100 | volume;
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ret = WM8960_WriteReg(handle, WM8960_LDAC, vol);
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ret = WM8960_WriteReg(handle, WM8960_RDAC, vol);
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break;
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case kWM8960_ModuleHP:
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vol = 0x100 | volume;
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ret = WM8960_WriteReg(handle, WM8960_LOUT1, vol);
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ret = WM8960_WriteReg(handle, WM8960_ROUT1, vol);
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break;
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case kWM8960_ModuleLineIn:
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vol = 0x100 | volume;
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ret = WM8960_WriteReg(handle, WM8960_LINVOL, vol);
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ret = WM8960_WriteReg(handle, WM8960_RINVOL, vol);
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break;
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case kWM8960_ModuleSpeaker:
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vol = 0x100 | volume;
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ret = WM8960_WriteReg(handle, WM8960_LOUT2, vol);
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ret = WM8960_WriteReg(handle, WM8960_ROUT2, vol);
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break;
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default:
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ret = kStatus_InvalidArgument;
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break;
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}
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return ret;
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}
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uint32_t WM8960_GetVolume(wm8960_handle_t *handle, wm8960_module_t module)
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{
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uint16_t vol = 0;
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switch (module)
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{
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case kWM8960_ModuleADC:
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WM8960_ReadReg(WM8960_LADC, &vol);
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vol &= 0xFF;
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break;
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case kWM8960_ModuleDAC:
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WM8960_ReadReg(WM8960_LDAC, &vol);
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vol &= 0xFF;
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break;
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case kWM8960_ModuleHP:
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WM8960_ReadReg(WM8960_LOUT1, &vol);
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vol &= 0x7F;
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break;
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case kWM8960_ModuleLineOut:
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WM8960_ReadReg(WM8960_LINVOL, &vol);
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vol &= 0x3F;
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break;
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default:
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vol = 0;
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break;
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}
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return vol;
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}
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status_t WM8960_SetMute(wm8960_handle_t *handle, wm8960_module_t module, bool isEnabled)
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{
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status_t ret = kStatus_Success;
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switch (module)
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{
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case kWM8960_ModuleADC:
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/*
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* Digital Mute
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*/
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if (isEnabled)
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{
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ret = WM8960_WriteReg(handle, WM8960_LADC, 0x100);
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ret = WM8960_WriteReg(handle, WM8960_RADC, 0x100);
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}
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else
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{
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ret = WM8960_WriteReg(handle, WM8960_LADC, 0x1C3);
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ret = WM8960_WriteReg(handle, WM8960_RADC, 0x1C3);
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}
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break;
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case kWM8960_ModuleDAC:
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/*
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* Digital mute
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*/
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if (isEnabled)
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{
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ret = WM8960_WriteReg(handle, WM8960_LDAC, 0x100);
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ret = WM8960_WriteReg(handle, WM8960_RDAC, 0x100);
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}
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else
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{
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ret = WM8960_WriteReg(handle, WM8960_LDAC, 0x1FF);
|
|
ret = WM8960_WriteReg(handle, WM8960_RDAC, 0x1FF);
|
|
}
|
|
break;
|
|
case kWM8960_ModuleHP:
|
|
/*
|
|
* Analog mute
|
|
*/
|
|
if (isEnabled)
|
|
{
|
|
ret = WM8960_WriteReg(handle, WM8960_LOUT1, 0x100);
|
|
ret = WM8960_WriteReg(handle, WM8960_ROUT1, 0x100);
|
|
}
|
|
else
|
|
{
|
|
ret = WM8960_WriteReg(handle, WM8960_LOUT1, 0x179);
|
|
ret = WM8960_WriteReg(handle, WM8960_ROUT1, 0x179);
|
|
}
|
|
break;
|
|
case kWM8960_ModuleLineOut:
|
|
break;
|
|
default:
|
|
ret = kStatus_InvalidArgument;
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
status_t WM8960_ConfigDataFormat(wm8960_handle_t *handle, uint32_t mclk, uint32_t sample_rate, uint8_t bits)
|
|
{
|
|
status_t retval = kStatus_Success;
|
|
|
|
switch (sample_rate)
|
|
{
|
|
case 8000:
|
|
retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0x1B0);
|
|
break;
|
|
case 11025:
|
|
retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0xD8);
|
|
break;
|
|
case 12000:
|
|
retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0x120);
|
|
break;
|
|
case 16000:
|
|
retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0xD8);
|
|
break;
|
|
case 22050:
|
|
retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0xD8);
|
|
break;
|
|
case 24000:
|
|
retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0x90);
|
|
break;
|
|
case 32000:
|
|
retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0x48);
|
|
break;
|
|
case 44100:
|
|
retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0xD8);
|
|
break;
|
|
case 48000:
|
|
retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0x00);
|
|
break;
|
|
default:
|
|
retval = kStatus_InvalidArgument;
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Slave mode (MS = 0), LRP = 0, 32bit WL, left justified (FORMAT[1:0]=0b01)
|
|
*/
|
|
switch (bits)
|
|
{
|
|
case 16:
|
|
retval = WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_WL_MASK,
|
|
WM8960_IFACE1_WL(WM8960_IFACE1_WL_16BITS));
|
|
break;
|
|
case 20:
|
|
retval = WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_WL_MASK,
|
|
WM8960_IFACE1_WL(WM8960_IFACE1_WL_20BITS));
|
|
break;
|
|
case 24:
|
|
retval = WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_WL_MASK,
|
|
WM8960_IFACE1_WL(WM8960_IFACE1_WL_24BITS));
|
|
break;
|
|
case 32:
|
|
retval = WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_WL_MASK,
|
|
WM8960_IFACE1_WL(WM8960_IFACE1_WL_32BITS));
|
|
break;
|
|
default:
|
|
retval = kStatus_InvalidArgument;
|
|
break;
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
status_t WM8960_SetJackDetect(wm8960_handle_t *handle, bool isEnabled)
|
|
{
|
|
uint8_t retval = 0;
|
|
uint16_t val = 0;
|
|
|
|
WM8960_ReadReg(WM8960_ADDCTL2, &val);
|
|
|
|
if (isEnabled)
|
|
{
|
|
val |= 0x40U;
|
|
}
|
|
else
|
|
{
|
|
val &= 0xCF;
|
|
}
|
|
|
|
retval = WM8960_WriteReg(handle, WM8960_ADDCTL2, val);
|
|
|
|
return retval;
|
|
}
|
|
|
|
status_t WM8960_WriteReg(wm8960_handle_t *handle, uint8_t reg, uint16_t val)
|
|
{
|
|
uint8_t cmd, buff;
|
|
uint8_t retval = 0;
|
|
|
|
/* The register address */
|
|
cmd = (reg << 1) | ((val >> 8U) & 0x0001U);
|
|
/* Data */
|
|
buff = val & 0xFF;
|
|
|
|
/* Copy data to cache */
|
|
reg_cache[reg] = val;
|
|
|
|
#if defined(FSL_FEATURE_SOC_LPI2C_COUNT) && (FSL_FEATURE_SOC_LPI2C_COUNT)
|
|
uint8_t data[2];
|
|
data[0] = cmd;
|
|
data[1] = buff;
|
|
retval = LPI2C_MasterStart(handle->base, WM8960_I2C_ADDR, kLPI2C_Write);
|
|
retval = LPI2C_MasterSend(handle->base, data, 2);
|
|
retval = LPI2C_MasterStop(handle->base);
|
|
#else
|
|
/* Config the I2C xfer */
|
|
handle->xfer.direction = kI2C_Write;
|
|
handle->xfer.subaddress = cmd;
|
|
handle->xfer.subaddressSize = 1U;
|
|
handle->xfer.data = &buff;
|
|
handle->xfer.dataSize = 1U;
|
|
|
|
retval = I2C_MasterTransferBlocking(handle->base, &handle->xfer);
|
|
#endif
|
|
|
|
if (retval != kStatus_Success)
|
|
{
|
|
return kStatus_Fail;
|
|
}
|
|
return kStatus_Success;
|
|
}
|
|
|
|
status_t WM8960_ReadReg(uint8_t reg, uint16_t *val)
|
|
{
|
|
if (reg >= WM8960_CACHEREGNUM)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
*val = reg_cache[reg];
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
status_t WM8960_ModifyReg(wm8960_handle_t *handle, uint8_t reg, uint16_t mask, uint16_t val)
|
|
{
|
|
uint8_t retval = 0;
|
|
uint16_t reg_val = 0;
|
|
retval = WM8960_ReadReg(reg, ®_val);
|
|
if (retval != kStatus_Success)
|
|
{
|
|
return kStatus_Fail;
|
|
}
|
|
reg_val &= (uint16_t)~mask;
|
|
reg_val |= val;
|
|
retval = WM8960_WriteReg(handle, reg, reg_val);
|
|
if (retval != kStatus_Success)
|
|
{
|
|
return kStatus_Fail;
|
|
}
|
|
return kStatus_Success;
|
|
}
|