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2322f0154e
Confirmed with milkv, only the sd card version is sold by default for duo in the market. The spi pins are provided through stamp holes, so that users can solder the corresponding components on their baseboard during secondary development. In order to simplify maintenance work, the mainline will only support the sd-card version and no longer support spinor/spinand. Updated config files the same in this patch. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
342 lines
8.1 KiB
C
342 lines
8.1 KiB
C
/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024/02/19 flyingcys first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "drv_pwm.h"
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#include "drv_pinmux.h"
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#include "drv_ioremap.h"
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#define DBG_LEVEL DBG_LOG
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#include <rtdbg.h>
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#define LOG_TAG "DRV.PWM"
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struct cvi_pwm_dev
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{
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struct rt_device_pwm device;
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const char *name;
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rt_ubase_t reg_base;
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};
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static const uint64_t count_unit = 100000000; // 100M count per second
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static const uint64_t NSEC_COUNT = 1000000000; // ns
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static void cvi_pwm_set_config(rt_ubase_t reg_base, struct rt_pwm_configuration *cfg)
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{
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unsigned long long duty_clk, period_clk;
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cvi_pwm_set_polarity_high_ch(reg_base, (cfg->channel & PWM_MAX_CH));
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duty_clk = (cfg->pulse * count_unit) / NSEC_COUNT;
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cvi_pwm_set_high_period_ch(reg_base, (cfg->channel & PWM_MAX_CH), duty_clk);
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period_clk = (cfg->period * count_unit) / NSEC_COUNT;
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cvi_pwm_set_period_ch(reg_base, (cfg->channel & PWM_MAX_CH), period_clk);
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cvi_pwm_output_en_ch(reg_base, cfg->channel & PWM_MAX_CH);
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}
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static void cvi_pwm_get_config(rt_ubase_t reg_base, struct rt_pwm_configuration *cfg)
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{
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unsigned long long duty_clk, period_clk;
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duty_clk = cvi_pwm_get_high_period_ch(reg_base, (cfg->channel & PWM_MAX_CH));
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cfg->pulse = duty_clk * NSEC_COUNT / count_unit;
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period_clk = cvi_pwm_get_period_ch(reg_base, (cfg->channel & PWM_MAX_CH));
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cfg->period = period_clk * NSEC_COUNT / count_unit;
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}
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static rt_err_t _pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg;
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struct cvi_pwm_dev *pwm_dev = (struct cvi_pwm_dev *)device->parent.user_data;
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unsigned long long duty_clk, period_clk;
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const uint64_t count_unit = 100000000; // 100M count per second
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const uint64_t NSEC_COUNT = 1000000000; // ns
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if (cfg->channel >= PWM_CHANNEL_NUM)
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return -RT_EINVAL;
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switch (cmd)
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{
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case PWM_CMD_ENABLE:
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cvi_pwm_start_en_ch(pwm_dev->reg_base, cfg->channel & PWM_MAX_CH);
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break;
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case PWM_CMD_DISABLE:
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cvi_pwm_start_dis_ch(pwm_dev->reg_base, cfg->channel & PWM_MAX_CH);
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break;
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case PWM_CMD_SET:
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cvi_pwm_set_config(pwm_dev->reg_base, cfg);
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break;
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case PWM_CMD_GET:
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cvi_pwm_get_config(pwm_dev->reg_base, cfg);
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break;
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case PWM_CMD_SET_PERIOD:
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period_clk = (cfg->period * count_unit) / NSEC_COUNT;
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cvi_pwm_set_period_ch(pwm_dev->reg_base, (cfg->channel & PWM_MAX_CH), period_clk);
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break;
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case PWM_CMD_SET_PULSE:
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duty_clk = (cfg->pulse * count_unit) / NSEC_COUNT;
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cvi_pwm_set_high_period_ch(pwm_dev->reg_base, (cfg->channel & PWM_MAX_CH), duty_clk);
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break;
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default:
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LOG_D("cmd: %x channel: %d period: %d pulse: %d", cmd, cfg->channel, cfg->period, cfg->pulse);
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break;
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}
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return RT_EOK;
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}
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const static struct rt_pwm_ops cvi_pwm_ops =
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{
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.control = &_pwm_control
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};
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static struct cvi_pwm_dev cvi_pwm[] =
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{
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#ifdef BSP_USING_PWM0
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{
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.name = "pwm0",
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.reg_base = CVI_PWM0_BASE,
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},
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#endif
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#ifdef BSP_USING_PWM1
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{
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.name = "pwm1",
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.reg_base = CVI_PWM1_BASE,
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},
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#endif
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#ifdef BSP_USING_PWM2
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{
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.name = "pwm2",
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.reg_base = CVI_PWM2_BASE,
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},
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#endif
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#ifdef BSP_USING_PWM3
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{
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.name = "pwm3",
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.reg_base = CVI_PWM3_BASE,
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},
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#endif
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};
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#if defined(BOARD_TYPE_MILKV_DUO)
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#ifdef BSP_USING_PWM0
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static const char *pinname_whitelist_pwm0[] = {
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NULL,
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};
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static const char *pinname_whitelist_pwm1[] = {
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NULL,
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};
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static const char *pinname_whitelist_pwm2[] = {
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NULL,
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};
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static const char *pinname_whitelist_pwm3[] = {
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NULL,
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};
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#endif
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#ifdef BSP_USING_PWM1
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static const char *pinname_whitelist_pwm4[] = {
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"SD1_D3",
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"UART0_TX",
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NULL,
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};
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static const char *pinname_whitelist_pwm5[] = {
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"SD1_D2",
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"UART0_RX",
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NULL,
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};
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static const char *pinname_whitelist_pwm6[] = {
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"SD1_D1",
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NULL,
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};
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static const char *pinname_whitelist_pwm7[] = {
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"SD1_D0",
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NULL,
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};
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#endif
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#ifdef BSP_USING_PWM2
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static const char *pinname_whitelist_pwm8[] = {
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"SD1_CMD",
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NULL,
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};
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static const char *pinname_whitelist_pwm9[] = {
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"SD1_CLK",
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NULL,
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};
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static const char *pinname_whitelist_pwm10[] = {
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"SD1_GPIO1",
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NULL,
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};
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static const char *pinname_whitelist_pwm11[] = {
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"SD1_GPIO0",
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NULL,
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};
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#endif
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#ifdef BSP_USING_PWM3
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static const char *pinname_whitelist_pwm12[] = {
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NULL,
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};
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static const char *pinname_whitelist_pwm13[] = {
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NULL,
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};
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static const char *pinname_whitelist_pwm14[] = {
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NULL,
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};
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static const char *pinname_whitelist_pwm15[] = {
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NULL,
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};
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#endif
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#elif defined(BOARD_TYPE_MILKV_DUO256M)
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#ifdef BSP_USING_PWM0
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static const char *pinname_whitelist_pwm0[] = {
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NULL,
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};
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static const char *pinname_whitelist_pwm1[] = {
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NULL,
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};
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static const char *pinname_whitelist_pwm2[] = {
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NULL,
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};
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static const char *pinname_whitelist_pwm3[] = {
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NULL,
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};
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#endif
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#ifdef BSP_USING_PWM1
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static const char *pinname_whitelist_pwm4[] = {
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"SD1_D3",
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"UART0_TX",
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NULL,
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};
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static const char *pinname_whitelist_pwm5[] = {
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"SD1_D2",
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"UART0_RX",
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NULL,
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};
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static const char *pinname_whitelist_pwm6[] = {
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"JTAG_CPU_TCK",
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"SD1_D1",
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NULL,
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};
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static const char *pinname_whitelist_pwm7[] = {
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"JTAG_CPU_TMS",
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"SD1_D0",
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NULL,
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};
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#endif
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#ifdef BSP_USING_PWM2
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static const char *pinname_whitelist_pwm8[] = {
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"SD1_CMD",
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NULL,
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};
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static const char *pinname_whitelist_pwm9[] = {
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"SD1_CLK",
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NULL,
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};
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static const char *pinname_whitelist_pwm10[] = {
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"PAD_MIPI_TXM1",
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NULL,
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};
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static const char *pinname_whitelist_pwm11[] = {
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"PAD_MIPI_TXP1",
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NULL,
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};
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#endif
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#ifdef BSP_USING_PWM3
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static const char *pinname_whitelist_pwm12[] = {
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NULL,
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};
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static const char *pinname_whitelist_pwm13[] = {
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NULL,
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};
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static const char *pinname_whitelist_pwm14[] = {
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NULL,
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};
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static const char *pinname_whitelist_pwm15[] = {
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NULL,
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};
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#endif
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#else
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#error "Unsupported board type!"
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#endif
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static void rt_hw_pwm_pinmux_config()
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{
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#ifdef BSP_USING_PWM0
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pinmux_config(BSP_PWM0_0_PINNAME, PWM_0, pinname_whitelist_pwm0);
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pinmux_config(BSP_PWM0_1_PINNAME, PWM_1, pinname_whitelist_pwm1);
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pinmux_config(BSP_PWM0_2_PINNAME, PWM_2, pinname_whitelist_pwm2);
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pinmux_config(BSP_PWM0_3_PINNAME, PWM_3, pinname_whitelist_pwm3);
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#endif /* BSP_USING_PWM0 */
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#ifdef BSP_USING_PWM1
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pinmux_config(BSP_PWM1_4_PINNAME, PWM_4, pinname_whitelist_pwm4);
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pinmux_config(BSP_PWM1_5_PINNAME, PWM_5, pinname_whitelist_pwm5);
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pinmux_config(BSP_PWM1_6_PINNAME, PWM_6, pinname_whitelist_pwm6);
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pinmux_config(BSP_PWM1_7_PINNAME, PWM_7, pinname_whitelist_pwm7);
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#endif /* BSP_USING_PWM1 */
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#ifdef BSP_USING_PWM2
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pinmux_config(BSP_PWM2_8_PINNAME, PWM_8, pinname_whitelist_pwm8);
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pinmux_config(BSP_PWM2_9_PINNAME, PWM_9, pinname_whitelist_pwm9);
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pinmux_config(BSP_PWM2_10_PINNAME, PWM_10, pinname_whitelist_pwm10);
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pinmux_config(BSP_PWM2_11_PINNAME, PWM_11, pinname_whitelist_pwm11);
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#endif /* BSP_USING_PWM2 */
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#ifdef BSP_USING_PWM3
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pinmux_config(BSP_PWM3_12_PINNAME, PWM_12, pinname_whitelist_pwm12);
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pinmux_config(BSP_PWM3_13_PINNAME, PWM_13, pinname_whitelist_pwm13);
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pinmux_config(BSP_PWM3_14_PINNAME, PWM_14, pinname_whitelist_pwm14);
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pinmux_config(BSP_PWM3_15_PINNAME, PWM_15, pinname_whitelist_pwm15);
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#endif /* BSP_USING_PWM3 */
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}
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int rt_hw_pwm_init(void)
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{
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int result = RT_EOK;
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uint8_t i;
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rt_hw_pwm_pinmux_config();
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for (i = 0; i < sizeof(cvi_pwm) / sizeof(cvi_pwm[0]); i++)
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{
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cvi_pwm[i].device.base = (rt_ubase_t)DRV_IOREMAP((void *)cvi_pwm[i].device.base, 0x1000);
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result = rt_device_pwm_register(&cvi_pwm[i].device, cvi_pwm[i].name, &cvi_pwm_ops, &cvi_pwm[i]);
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if (result != RT_EOK)
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{
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LOG_E("device %s register failed", cvi_pwm[i].name);
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return -RT_ERROR;
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}
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}
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return RT_EOK;
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}
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INIT_DEVICE_EXPORT(rt_hw_pwm_init);
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