224 lines
10 KiB
C
224 lines
10 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-05-25 RT-Thread the first version
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*/
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#ifndef __DRV_PL041_H__
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#define __DRV_PL041_H__
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#define PL041_BASE_ADDR (0x10004000)
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/* offsets in CTRL_CH */
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#define AACI_RXCR 0x00 /* 29 bits Control Rx FIFO */
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#define AACI_TXCR 0x04 /* 17 bits Control Tx FIFO */
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#define AACI_SR 0x08 /* 12 bits Status */
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#define AACI_ISR 0x0C /* 7 bits Int Status */
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#define AACI_IE 0x10 /* 7 bits Int Enable */
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/* both for AACI_RXCR and AACI_TXCR */
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#define AACI_CR_FEN (1 << 16) /* fifo enable */
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#define AACI_CR_COMPACT (1 << 15) /* compact mode */
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#define AACI_CR_SZ16 (0 << 13) /* 16 bits */
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#define AACI_CR_SZ18 (1 << 13) /* 18 bits */
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#define AACI_CR_SZ20 (2 << 13) /* 20 bits */
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#define AACI_CR_SZ12 (3 << 13) /* 12 bits */
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#define AACI_CR_SL12 (1 << 12)
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#define AACI_CR_SL11 (1 << 11)
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#define AACI_CR_SL10 (1 << 10)
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#define AACI_CR_SL9 (1 << 9)
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#define AACI_CR_SL8 (1 << 8)
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#define AACI_CR_SL7 (1 << 7)
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#define AACI_CR_SL6 (1 << 6)
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#define AACI_CR_SL5 (1 << 5)
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#define AACI_CR_SL4 (1 << 4)
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#define AACI_CR_SL3 (1 << 3)
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#define AACI_CR_SL2 (1 << 2)
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#define AACI_CR_SL1 (1 << 1)
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#define AACI_CR_EN (1 << 0) /* receive enable */
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/* status register bits */
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#define AACI_SR_RXTOFE (1 << 11) /* rx timeout fifo empty */
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#define AACI_SR_TXTO (1 << 10) /* rx timeout fifo nonempty */
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#define AACI_SR_TXU (1 << 9) /* tx underrun */
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#define AACI_SR_RXO (1 << 8) /* rx overrun */
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#define AACI_SR_TXB (1 << 7) /* tx busy */
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#define AACI_SR_RXB (1 << 6) /* rx busy */
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#define AACI_SR_TXFF (1 << 5) /* tx fifo full */
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#define AACI_SR_RXFF (1 << 4) /* rx fifo full */
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#define AACI_SR_TXHE (1 << 3) /* tx fifo half empty */
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#define AACI_SR_RXHF (1 << 2) /* rx fifo half full */
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#define AACI_SR_TXFE (1 << 1) /* tx fifo empty */
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#define AACI_SR_RXFE (1 << 0) /* rx fifo empty */
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#define AACI_ISR_RXTOFEINTR (1 << 6) /* rx fifo empty */
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#define AACI_ISR_URINTR (1 << 5) /* tx underflow */
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#define AACI_ISR_ORINTR (1 << 4) /* rx overflow */
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#define AACI_ISR_RXINTR (1 << 3) /* rx fifo */
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#define AACI_ISR_TXINTR (1 << 2) /* tx fifo intr */
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#define AACI_ISR_RXTOINTR (1 << 1) /* rx timeout */
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#define AACI_ISR_TXCINTR (1 << 0) /* tx complete */
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/* interrupt enable */
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#define AACI_IE_RXTOIE (1 << 6) /*rx timeout interrupt enable*/
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#define AACI_IE_URIE (1 << 5) /*Transmit underrun interrupt enable*/
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#define AACI_IE_ORIE (1 << 4) /*Overrun receive interrupt enable*/
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#define AACI_IE_RXIE (1 << 3) /*Receive interrupt enable*/
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#define AACI_IE_TXIE (1 << 2) /*Transmit interrupt enable*/
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#define AACI_IE_RXTIE (1 << 1) /*Receive timeout interrupt enable*/
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#define AACI_IE_TXCIE (1 << 0) /*Transmit complete interrupt enable*/
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/* interrupt status */
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#define AACI_ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */
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#define AACI_ISR_UR (1 << 5) /* tx fifo underrun */
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#define AACI_ISR_OR (1 << 4) /* rx fifo overrun */
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#define AACI_ISR_RX (1 << 3) /* rx interrupt status */
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#define AACI_ISR_TX (1 << 2) /* tx interrupt status */
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#define AACI_ISR_RXTO (1 << 1) /* rx timeout */
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#define AACI_ISR_TXC (1 << 0) /* tx complete */
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/* interrupt enable */
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#define AACI_IE_RXTOFE (1 << 6) /* rx timeout fifo empty */
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#define AACI_IE_UR (1 << 5) /* tx fifo underrun */
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#define AACI_IE_OR (1 << 4) /* rx fifo overrun */
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#define AACI_IE_RX (1 << 3) /* rx interrupt status */
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#define AACI_IE_TX (1 << 2) /* tx interrupt status */
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#define AACI_IE_RXTO (1 << 1) /* rx timeout */
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#define AACI_IE_TXC (1 << 0) /* tx complete */
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/* slot flag register bits */
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#define AACI_SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */
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#define AACI_SLFR_RGPIOINTR (1 << 12) /* raw gpio interrupt */
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#define AACI_SLFR_12TXE (1 << 11) /* slot 12 tx empty */
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#define AACI_SLFR_12RXV (1 << 10) /* slot 12 rx valid */
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#define AACI_SLFR_2TXE (1 << 9) /* slot 2 tx empty */
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#define AACI_SLFR_2RXV (1 << 8) /* slot 2 rx valid */
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#define AACI_SLFR_1TXE (1 << 7) /* slot 1 tx empty */
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#define AACI_SLFR_1RXV (1 << 6) /* slot 1 rx valid */
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#define AACI_SLFR_12TXB (1 << 5) /* slot 12 tx busy */
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#define AACI_SLFR_12RXB (1 << 4) /* slot 12 rx busy */
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#define AACI_SLFR_2TXB (1 << 3) /* slot 2 tx busy */
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#define AACI_SLFR_2RXB (1 << 2) /* slot 2 rx busy */
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#define AACI_SLFR_1TXB (1 << 1) /* slot 1 tx busy */
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#define AACI_SLFR_1RXB (1 << 0) /* slot 1 rx busy */
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/* Interrupt clear register */
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#define AACI_ICLR_RXTOFEC4 (1 << 12) /* Receive timeout FIFO empty clear */
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#define AACI_ICLR_RXTOFEC3 (1 << 11) /* Receive timeout FIFO empty clear */
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#define AACI_ICLR_RXTOFEC2 (1 << 10) /* Receive timeout FIFO empty clear */
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#define AACI_ICLR_RXTOFEC1 (1 << 9) /* Receive timeout FIFO empty clear */
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#define AACI_ICLR_TXUEC4 (1 << 8) /* Transmit underrun error clear */
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#define AACI_ICLR_TXUEC3 (1 << 7) /* Transmit underrun error clear */
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#define AACI_ICLR_TXUEC2 (1 << 6) /* Transmit underrun error clear*/
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#define AACI_ICLR_TXUEC1 (1 << 5) /* Transmit underrun error clear */
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#define AACI_ICLR_RXOEC4 (1 << 4) /* Receive overrun error clear */
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#define AACI_ICLR_RXOEC3 (1 << 3) /* Receive overrun error clear */
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#define AACI_ICLR_RXOEC2 (1 << 2) /* Receive overrun error clear */
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#define AACI_ICLR_RXOEC1 (1 << 1) /* Receive overrun error clear */
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#define AACI_ICLR_WISC (1 << 0) /* Wake-up interrupt status clear */
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/* Main control register bits AACI_MAINCR */
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#define AACI_MAINCR_SCRA(x) ((x) << 10) /* secondary codec reg access */
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#define AACI_MAINCR_DMAEN (1 << 9) /* dma enable */
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#define AACI_MAINCR_SL12TXEN (1 << 8) /* slot 12 transmit enable */
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#define AACI_MAINCR_SL12RXEN (1 << 7) /* slot 12 receive enable */
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#define AACI_MAINCR_SL2TXEN (1 << 6) /* slot 2 transmit enable */
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#define AACI_MAINCR_SL2RXEN (1 << 5) /* slot 2 receive enable */
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#define AACI_MAINCR_SL1TXEN (1 << 4) /* slot 1 transmit enable */
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#define AACI_MAINCR_SL1RXEN (1 << 3) /* slot 1 receive enable */
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#define AACI_MAINCR_LPM (1 << 2) /* low power mode */
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#define AACI_MAINCR_LOOPBK (1 << 1) /* loopback */
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#define AACI_MAINCR_IE (1 << 0) /* aaci interface enable */
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/* Reset register bits. P65 */
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#define RESET_NRST (1 << 0)
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/* Sync register bits. P65 */
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#define SYNC_FORCE (1 << 0)
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/* Main flag register bits. P66 */
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#define MAINFR_TXB (1 << 1) /* transmit busy */
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#define MAINFR_RXB (1 << 0) /* receive busy */
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#define PL041_CHANNEL_LEFT_DAC (0x1 << 3)
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#define PL041_CHANNEL_RIGHT_DAC (0x1 << 3)
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#define PL041_CHANNEL_LEFT_ADC (0x1 << 3)
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#define PL041_CHANNEL_RIGHT_ADC (0x1 << 3)
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struct reg_pl041
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{
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volatile rt_uint32_t rxcr1; /* 0x000 */
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volatile rt_uint32_t txcr1; /* 0x004 */
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volatile rt_uint32_t sr1; /* 0x008 */
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volatile rt_uint32_t isr1; /* 0x00c */
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volatile rt_uint32_t iie1; /* 0x010 */
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volatile rt_uint32_t rxcr2; /* 0x014 */
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volatile rt_uint32_t txcr2; /* 0x018 */
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volatile rt_uint32_t sr2; /* 0x01c */
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volatile rt_uint32_t isr2; /* 0x020 */
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volatile rt_uint32_t iie2; /* 0x024 */
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volatile rt_uint32_t rxcr3; /* 0x028 */
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volatile rt_uint32_t txcr3; /* 0x02c */
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volatile rt_uint32_t sr3; /* 0x030 */
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volatile rt_uint32_t isr3; /* 0x034 */
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volatile rt_uint32_t iie3; /* 0x038 */
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volatile rt_uint32_t rxcr4; /* 0x03c */
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volatile rt_uint32_t txcr4; /* 0x040 */
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volatile rt_uint32_t sr4; /* 0x044 */
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volatile rt_uint32_t isr4; /* 0x048 */
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volatile rt_uint32_t iie4; /* 0x04c */
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volatile rt_uint32_t sl1rx; /* 0x050 */
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volatile rt_uint32_t sl1tx; /* 0x054 */
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volatile rt_uint32_t sl2rx; /* 0x058 */
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volatile rt_uint32_t sl2tx; /* 0x05c */
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volatile rt_uint32_t sl12rx; /* 0x060 */
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volatile rt_uint32_t sl12tx; /* 0x064 */
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volatile rt_uint32_t slfr; /* 0x068 */
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volatile rt_uint32_t slistat; /* 0x06c */
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volatile rt_uint32_t slien; /* 0x070 */
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volatile rt_uint32_t intclr; /* 0x074 */
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volatile rt_uint32_t maincr; /* 0x078 */
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volatile rt_uint32_t reset; /* 0x07c */
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volatile rt_uint32_t sync; /* 0x080 */
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volatile rt_uint32_t allints; /* 0x084 */
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volatile rt_uint32_t mainfr; /* 0x088 */
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volatile rt_uint32_t res08c;
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volatile rt_uint32_t dr1[8]; /* 0x090 */
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volatile rt_uint32_t dr2[8]; /* 0x0b0 */
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volatile rt_uint32_t dr3[8]; /* 0x0d0 */
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volatile rt_uint32_t dr4[8]; /* 0x0f0 */
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};
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typedef struct reg_pl041 *reg_pl041_t;
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#define PL041 ((reg_pl041_t)PL041_BASE_ADDR)
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struct pl041_cfg
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{
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rt_uint32_t itype;
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rt_uint32_t otype;
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int vol;
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int rate;
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};
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typedef struct pl041_cfg *pl041_cfg_t;
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typedef void (*pl041_irq_fun_t)(rt_uint32_t status, void * user_data);
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rt_err_t aaci_pl041_init(void);
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void aaci_ac97_write(rt_uint16_t reg, rt_uint16_t val);
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rt_uint16_t aaci_ac97_read(rt_uint16_t reg);
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int aaci_pl041_channel_cfg(int channel, pl041_cfg_t cfg);
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int aaci_pl041_channel_write(int channel, rt_uint16_t *buff, int count);
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int aaci_pl041_channel_read(int channel, rt_uint16_t *buff, int count);
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int aaci_pl041_channel_enable(int channel);
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int aaci_pl041_channel_disable(int channel);
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rt_err_t aaci_pl041_irq_register(int channel, pl041_irq_fun_t fun, void *user_data);
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rt_err_t aaci_pl041_irq_unregister(int channel);
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void aaci_pl041_irq_disable(int channel, rt_uint32_t vector);
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void aaci_pl041_irq_enable(int channel, rt_uint32_t vector);
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#endif
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