126 lines
4.0 KiB
C
126 lines
4.0 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-05-12 RT-Thread the first version
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*/
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#ifndef __MMU_H_
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#define __MMU_H_
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#include <rtthread.h>
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#include <mm_aspace.h>
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/* normal memory wra mapping type */
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#define NORMAL_MEM 0
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/* normal nocache memory mapping type */
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#define NORMAL_NOCACHE_MEM 1
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/* device mapping type */
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#define DEVICE_MEM 2
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struct mem_desc
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{
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unsigned long vaddr_start;
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unsigned long vaddr_end;
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unsigned long paddr_start;
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unsigned long attr;
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struct rt_varea varea;
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};
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#define MMU_AF_SHIFT 10
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#define MMU_SHARED_SHIFT 8
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#define MMU_AP_SHIFT 6
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#define MMU_MA_SHIFT 2
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#define MMU_AP_KAUN 0UL /* kernel r/w, user none */
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#define MMU_AP_KAUA 1UL /* kernel r/w, user r/w */
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#define MMU_AP_KRUN 2UL /* kernel r, user none */
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#define MMU_AP_KRUR 3UL /* kernel r, user r */
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#define MMU_MAP_CUSTOM(ap, mtype) \
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((0x1UL << MMU_AF_SHIFT) | (0x2UL << MMU_SHARED_SHIFT) | \
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((ap) << MMU_AP_SHIFT) | ((mtype) << MMU_MA_SHIFT))
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#define MMU_MAP_K_RO MMU_MAP_CUSTOM(MMU_AP_KRUN, NORMAL_MEM)
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#define MMU_MAP_K_RWCB MMU_MAP_CUSTOM(MMU_AP_KAUN, NORMAL_MEM)
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#define MMU_MAP_K_RW MMU_MAP_CUSTOM(MMU_AP_KAUN, NORMAL_NOCACHE_MEM)
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#define MMU_MAP_K_DEVICE MMU_MAP_CUSTOM(MMU_AP_KAUN, DEVICE_MEM)
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#define MMU_MAP_U_RO MMU_MAP_CUSTOM(MMU_AP_KRUR, NORMAL_NOCACHE_MEM)
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#define MMU_MAP_U_RWCB MMU_MAP_CUSTOM(MMU_AP_KAUA, NORMAL_MEM)
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#define MMU_MAP_U_RW MMU_MAP_CUSTOM(MMU_AP_KAUA, NORMAL_NOCACHE_MEM)
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#define MMU_MAP_U_DEVICE MMU_MAP_CUSTOM(MMU_AP_KAUA, DEVICE_MEM)
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#define ARCH_SECTION_SHIFT 21
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#define ARCH_SECTION_SIZE (1 << ARCH_SECTION_SHIFT)
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#define ARCH_SECTION_MASK (ARCH_SECTION_SIZE - 1)
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#define ARCH_PAGE_SHIFT 12
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#define ARCH_PAGE_SIZE (1 << ARCH_PAGE_SHIFT)
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#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
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#define ARCH_PAGE_TBL_SHIFT 12
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#define ARCH_PAGE_TBL_SIZE (1 << ARCH_PAGE_TBL_SHIFT)
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#define ARCH_PAGE_TBL_MASK (ARCH_PAGE_TBL_SIZE - 1)
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#define ARCH_VADDR_WIDTH 48
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#define ARCH_ADDRESS_WIDTH_BITS 64
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#define MMU_MAP_ERROR_VANOTALIGN -1
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#define MMU_MAP_ERROR_PANOTALIGN -2
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#define MMU_MAP_ERROR_NOPAGE -3
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#define MMU_MAP_ERROR_CONFLICT -4
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#define ARCH_MAP_FAILED ((void *)0x1ffffffffffff)
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struct rt_aspace;
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void rt_hw_mmu_ktbl_set(unsigned long tbl);
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void rt_hw_mem_setup_early(unsigned long *tbl0, unsigned long *tbl1,
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unsigned long size, unsigned long pv_off);
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void rt_hw_mmu_setup(struct rt_aspace *aspace, struct mem_desc *mdesc,
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int desc_nr);
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int rt_hw_mmu_map_init(struct rt_aspace *aspace, void *v_address,
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rt_size_t size, rt_size_t *vtable, rt_size_t pv_off);
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void *rt_hw_mmu_map(struct rt_aspace *aspace, void *v_addr, void *p_addr,
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size_t size, size_t attr);
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void rt_hw_mmu_unmap(struct rt_aspace *aspace, void *v_addr, size_t size);
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void rt_hw_aspace_switch(struct rt_aspace *aspace);
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void *rt_hw_mmu_v2p(struct rt_aspace *aspace, void *vaddr);
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void rt_hw_mmu_kernel_map_init(struct rt_aspace *aspace, rt_size_t vaddr_start,
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rt_size_t size);
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void rt_hw_mmu_ktbl_set(unsigned long tbl);
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static inline void *rt_hw_mmu_tbl_get()
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{
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uintptr_t tbl;
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__asm__ volatile("MRS %0, TTBR0_EL1" : "=r"(tbl));
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return (void *)(tbl & ((1ul << 48) - 2));
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}
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static inline void *rt_hw_mmu_kernel_v2p(void *v_addr)
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{
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rt_ubase_t par;
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void *paddr;
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asm volatile("at s1e1w, %0"::"r"(v_addr):"memory");
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asm volatile("mrs %0, par_el1":"=r"(par)::"memory");
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if (par & 0x1)
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{
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paddr = ARCH_MAP_FAILED;
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}
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else
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{
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#define MMU_ADDRESS_MASK 0x0000fffffffff000UL
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par &= MMU_ADDRESS_MASK;
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par |= (rt_ubase_t)v_addr & ARCH_PAGE_MASK;
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paddr = (void *)par;
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}
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return paddr;
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}
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int rt_hw_mmu_control(struct rt_aspace *aspace, void *vaddr, size_t size,
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enum rt_mmu_cntl cmd);
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#endif
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