267 lines
5.7 KiB
C
267 lines
5.7 KiB
C
/**************************************************
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*
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* This file shall be included in appropriate CMSIS header
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* files, to provide required functions and intrinsics when
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* building with the IAR C/C++ Compiler for ARM (iccarm).
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*
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* Copyright 2011 IAR Systems. All rights reserved.
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*
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* $Revision: 78346 $
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*
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**************************************************/
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#ifndef __CMSIS_IAR_H__
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#define __CMSIS_IAR_H__
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#ifndef __ICCARM__
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#error This file should only be compiled by ICCARM
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#endif
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#pragma system_include
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#include <intrinsics.h>
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#if (__CORE__ == __ARM6M__)
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/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
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#define __CLZ __cmsis_iar_clz
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#define __SSAT __cmsis_iar_ssat
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#endif
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#pragma diag_suppress=Pe940
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#pragma diag_suppress=Pe177
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#define __enable_irq __enable_interrupt
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#define __disable_irq __disable_interrupt
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#define __NOP __no_operation
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#if (__VER__ >= 6040000) /* If iccarm version is 6.40.x or newer ---------- */
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#define __BKPT(value) asm volatile ("BKPT\t%0" : : "i"(value))
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#endif
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#if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */
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#if (__VER__ < 6010002) /* If iccarm version is older than 6.10.2 ---------- */
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static uint32_t __get_APSR(void)
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{
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__ASM("mrs r0, apsr");
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}
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static uint32_t __get_xPSR(void)
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{
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__ASM("mrs r0, psr"); /* assembler does not know "xpsr" */
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}
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#endif /* __VER__ < 6010002 */
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static uint32_t __get_IPSR(void)
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{
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__ASM("mrs r0, ipsr");
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}
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static uint32_t __get_PSR(void)
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{
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__ASM("mrs r0, psr");
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}
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static uint32_t __get_PSP(void)
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{
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__ASM("mrs r0, psp");
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}
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static void __set_PSP(uint32_t topOfProcStack)
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{
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__ASM("msr psp, r0");
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}
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static uint32_t __get_MSP(void)
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{
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__ASM("mrs r0, msp");
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}
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static void __set_MSP(uint32_t topOfMainStack)
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{
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__ASM("msr msp, r0");
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}
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static __INLINE void __WFI(void)
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{
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__ASM ("wfi");
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}
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static __INLINE void __WFE(void)
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{
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__ASM ("wfe");
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}
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static __INLINE void __SEV(void)
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{
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__ASM ("sev");
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}
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static uint32_t __REV16(uint32_t value)
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{
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__ASM("rev16 r0, r0");
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}
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#else /* __VER__ < 6020000 */
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static uint32_t __get_xPSR(void)
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{
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return __get_PSR(); /* __get_PSR() intrinsic introduced in iccarm 6.20 */
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}
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#endif /* __VER__ < 6020000 */
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#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
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#if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */
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static __INLINE void __enable_fault_irq(void)
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{
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__ASM ("cpsie f");
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}
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static __INLINE void __disable_fault_irq(void)
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{
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__ASM ("cpsid f");
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}
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static uint32_t __RBIT(uint32_t value)
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{
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__ASM("rbit r0, r0");
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}
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static uint8_t __LDREXB(volatile uint8_t *addr)
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{
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__ASM("ldrexb r0, [r0]");
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}
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static uint16_t __LDREXH(volatile uint16_t *addr)
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{
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__ASM("ldrexh r0, [r0]");
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}
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static uint32_t __LDREXW(volatile uint32_t *addr)
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{
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__ASM("ldrex r0, [r0]");
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}
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static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
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{
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__ASM("strexb r0, r0, [r1]");
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}
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static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
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{
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__ASM("strexh r0, r0, [r1]");
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}
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static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
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{
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__ASM("strex r0, r0, [r1]");
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}
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static __INLINE void __CLREX(void)
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{
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__ASM ("clrex");
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}
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#else /* __VER__ >= 6020000 --------------------- */
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#define __LDREXW __LDREX
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#define __STREXW __STREX
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#define __enable_fault_irq __enable_fiq
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#define __disable_fault_irq __disable_fiq
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#endif /* __VER__ < 6020000 */
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#endif /* (__CORTEX_M >= 0x03) */
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#if (__CORTEX_M == 0x04) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
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#if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */
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static uint32_t __get_FPSCR(void)
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{
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#if (__FPU_PRESENT == 1) /* __FPU_PRESENT is defined in the device header file, if present in current device. */
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__ASM("vmrs r0, fpscr");
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#else
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return(0);
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#endif
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}
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static void __set_FPSCR(uint32_t fpscr)
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{
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#if (__FPU_PRESENT == 1) /* __FPU_PRESENT is defined in the device header file, if present in current device. */
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__ASM("vmsr fpscr, r0");
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#endif
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}
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#endif /* __VER__ < 6020000 */
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#endif /* (__CORTEX_M == 0x04) */
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#if (__VER__ >= 7000000) /* If iccarm version is 7.x or newer ---------- */
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#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
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static __INLINE uint32_t __RRX(uint32_t value)
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{
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uint32_t result;
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__ASM("RRX %0, %1" : "=r"(result) : "r" (value) );
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return(result);
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}
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static __INLINE uint8_t __LDRBT(volatile uint8_t *addr)
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{
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uint32_t result;
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__ASM("LDRBT %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
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return ((uint8_t) result);
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}
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static __INLINE uint16_t __LDRHT(volatile uint16_t *addr)
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{
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uint32_t result;
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__ASM("LDRHT %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
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return ((uint16_t) result);
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}
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static __INLINE uint32_t __LDRT(volatile uint32_t *addr)
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{
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uint32_t result;
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__ASM("LDRT %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
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return(result);
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}
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static __INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
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{
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__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory" );
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}
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static __INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
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{
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__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory" );
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}
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static __INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
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{
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__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory" );
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}
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#endif /* (__CORTEX_M >= 0x03) */
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#endif /* __VER__ >= 7000000 */
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static __INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
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{
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return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
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}
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#pragma diag_default=Pe940
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#pragma diag_default=Pe177
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#endif /* __CMSIS_IAR_H__ */
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