458 lines
8.9 KiB
C
458 lines
8.9 KiB
C
/*
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* File : mmu.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2012-01-10 bernard porting to AM1808
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*/
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#include <rtthread.h>
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#include "am33xx.h"
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#define DESC_SEC (0x2)
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#define CB (3<<2) //cache_on, write_back
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#define CNB (2<<2) //cache_on, write_through
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#define NCB (1<<2) //cache_off,WR_BUF on
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#define NCNB (0<<2) //cache_off,WR_BUF off
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#define AP_RW (3<<10) //supervisor=RW, user=RW
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#define AP_RO (2<<10) //supervisor=RW, user=RO
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#define DOMAIN_FAULT (0x0)
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#define DOMAIN_CHK (0x1)
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#define DOMAIN_NOTCHK (0x3)
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#define DOMAIN0 (0x0<<5)
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#define DOMAIN1 (0x1<<5)
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#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
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#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
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#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */
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#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */
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#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
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#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
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#ifdef __CC_ARM
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void mmu_setttbase(rt_uint32_t i)
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{
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register rt_uint32_t value;
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/* Invalidates all TLBs.Domain access is selected as
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* client by configuring domain access register,
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* in that case access controlled by permission value
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* set by page table entry
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*/
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value = 0;
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__asm volatile
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{
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mcr p15, 0, value, c8, c7, 0
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}
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value = 0x55555555;
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__asm volatile
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{
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mcr p15, 0, value, c3, c0, 0
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mcr p15, 0, i, c2, c0, 0
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}
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}
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void mmu_set_domain(rt_uint32_t i)
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{
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__asm volatile
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{
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mcr p15,0, i, c3, c0, 0
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}
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}
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void mmu_enable()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x01
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x01
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_enable_icache()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x1000
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_enable_dcache()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x04
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable_icache()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x1000
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable_dcache()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x04
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_enable_alignfault()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x02
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable_alignfault()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x02
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_clean_invalidated_cache_index(int index)
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{
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__asm volatile
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{
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mcr p15, 0, index, c7, c14, 2
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}
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}
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void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~0x1f;
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while(ptr < buffer + size)
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{
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__asm volatile
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{
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MCR p15, 0, ptr, c7, c14, 1
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}
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ptr += 32;
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}
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}
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void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~0x1f;
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while (ptr < buffer + size)
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{
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__asm volatile
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{
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MCR p15, 0, ptr, c7, c10, 1
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}
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ptr += 32;
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}
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}
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void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~0x1f;
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while (ptr < buffer + size)
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{
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__asm volatile
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{
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MCR p15, 0, ptr, c7, c6, 1
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}
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ptr += 32;
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}
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}
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void mmu_invalidate_tlb()
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{
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register rt_uint32_t value;
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value = 0;
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__asm volatile
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{
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mcr p15, 0, value, c8, c7, 0
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}
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}
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void mmu_invalidate_icache()
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{
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register rt_uint32_t value;
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value = 0;
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__asm volatile
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{
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mcr p15, 0, value, c7, c5, 0
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}
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}
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#elif defined(__GNUC__)
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void mmu_setttbase(register rt_uint32_t i)
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{
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register rt_uint32_t value;
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/* Invalidates all TLBs.Domain access is selected as
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* client by configuring domain access register,
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* in that case access controlled by permission value
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* set by page table entry
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*/
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value = 0;
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asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
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value = 0x55555555;
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asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
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asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
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}
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void mmu_set_domain(register rt_uint32_t i)
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{
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asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
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}
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void mmu_enable()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= 0x1;
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~0x1;
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_icache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 12);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_dcache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 2);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_icache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 12);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_dcache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 2);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_alignfault()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 1);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_alignfault()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 1);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_clean_invalidated_cache_index(int index)
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{
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asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
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}
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void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~0x1f;
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while (ptr < buffer + size)
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{
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asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
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ptr += 32;
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}
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}
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void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~0x1f;
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while (ptr < buffer + size)
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{
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asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
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ptr += 32;
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}
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}
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void mmu_invalidate_tlb()
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{
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asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
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}
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void mmu_invalidate_icache()
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{
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asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
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}
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#endif
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/* level1 page table */
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static volatile unsigned int _page_table[4*1024] __attribute__((aligned(16*1024)));
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void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrStart, rt_uint32_t attr)
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{
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volatile rt_uint32_t *pTT;
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volatile int i,nSec;
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pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20);
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nSec=(vaddrEnd>>20)-(vaddrStart>>20);
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for(i=0;i<=nSec;i++)
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{
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*pTT = attr |(((paddrStart>>20)+i)<<20);
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pTT++;
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}
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}
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void rt_hw_mmu_init(void)
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{
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/* disable I/D cache */
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mmu_disable_dcache();
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mmu_disable_icache();
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mmu_disable();
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mmu_invalidate_tlb();
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/* set page table */
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mmu_setmtt(0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB); /* None cached for 4G memory */
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mmu_setmtt(0xC0000000, 0xC8000000-1, 0xC0000000, RW_CB); /* 128M cached DDR memory */
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mmu_setmtt(0xD0000000, 0xD8000000-1, 0xC0000000, RW_NCNB); /* 128M none-cached DDR memory */
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mmu_setmtt(0x80000000, 0x80020000-1, 0x80000000, RW_CB); /* 128k OnChip memory */
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/* set MMU table address */
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mmu_setttbase((rt_uint32_t)_page_table);
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/* enables MMU */
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mmu_enable();
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/* enable Instruction Cache */
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mmu_enable_icache();
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/* enable Data Cache */
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mmu_enable_dcache();
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}
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