465 lines
9.3 KiB
C
465 lines
9.3 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-05-16 shelton first version
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*/
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#include "board.h"
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#include "drv_hwtimer.h"
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//#define DRV_DEBUG
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#define LOG_TAG "drv.hwtimer"
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#include <drv_log.h>
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#ifdef BSP_USING_HWTIMER
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enum
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{
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#ifdef BSP_USING_HWTMR1
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TMR1_INDEX,
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#endif
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#ifdef BSP_USING_HWTMR2
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TMR2_INDEX,
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#endif
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#ifdef BSP_USING_HWTMR3
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TMR3_INDEX,
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#endif
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#ifdef BSP_USING_HWTMR4
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TMR4_INDEX,
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#endif
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#ifdef BSP_USING_HWTMR5
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TMR5_INDEX,
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#endif
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#ifdef BSP_USING_HWTMR6
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TMR6_INDEX,
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#endif
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#ifdef BSP_USING_HWTMR7
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TMR7_INDEX,
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#endif
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#ifdef BSP_USING_HW_TMR8
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TMR8_INDEX,
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#endif
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#ifdef BSP_USING_HWTMR9
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TMR9_INDEX,
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#endif
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#ifdef BSP_USING_HWTMR10
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TMR10_INDEX,
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#endif
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#ifdef BSP_USING_HWTMR11
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TMR11_INDEX,
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#endif
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#ifdef BSP_USING_HWTMR12
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TMR12_INDEX,
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#endif
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#ifdef BSP_USING_HWTMR13
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TMR13_INDEX,
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#endif
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#ifdef BSP_USING_HWTMR14
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TMR14_INDEX,
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#endif
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#ifdef BSP_USING_HWTMR15
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TMR15_INDEX,
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#endif
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};
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struct at32_hwtimer
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{
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rt_hwtimer_t tmr_device;
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tmr_type* tmr_x;
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IRQn_Type tmr_irqn;
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char *name;
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};
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static struct at32_hwtimer at32_hwtimer_obj[] =
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{
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#ifdef BSP_USING_HWTMR1
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TMR1_CONFIG,
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#endif
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#ifdef BSP_USING_HWTMR2
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TMR2_CONFIG,
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#endif
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#ifdef BSP_USING_HWTMR3
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TMR3_CONFIG,
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#endif
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#ifdef BSP_USING_HWTMR4
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TMR4_CONFIG,
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#endif
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#ifdef BSP_USING_HWTMR5
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TMR5_CONFIG,
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#endif
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#ifdef BSP_USING_HWTMR6
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TMR6_CONFIG,
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#endif
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#ifdef BSP_USING_HWTMR7
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TMR7_CONFIG,
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#endif
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#ifdef BSP_USING_HWTMR8
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TMR8_CONFIG,
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#endif
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#ifdef BSP_USING_HWTMR9
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TMR9_CONFIG,
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#endif
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#ifdef BSP_USING_HWTMR10
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TMR10_CONFIG,
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#endif
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#ifdef BSP_USING_HWTMR11
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TMR11_CONFIG,
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#endif
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#ifdef BSP_USING_HWTMR12
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TMR12_CONFIG,
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#endif
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#ifdef BSP_USING_HWTMR13
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TMR13_CONFIG,
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#endif
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#ifdef BSP_USING_HWTMR14
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TMR14_CONFIG,
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#endif
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#ifdef BSP_USING_HWTMR15
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TMR15_CONFIG,
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#endif
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};
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static void tmr_pclk_get(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_doubler)
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{
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crm_clocks_freq_type clocks_struct;
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*pclk1_doubler = 1;
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*pclk2_doubler = 1;
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crm_clocks_freq_get(&clocks_struct);
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if(clocks_struct.ahb_freq != clocks_struct.apb1_freq)
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{
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*pclk1_doubler = 2;
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}
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if(clocks_struct.ahb_freq != clocks_struct.apb2_freq)
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{
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*pclk2_doubler = 2;
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}
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}
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static void at32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
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{
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crm_clocks_freq_type clocks_struct;
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rt_uint32_t pclk1_doubler = 0, pclk2_doubler = 0;
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rt_uint32_t prescaler_value = 0, tmr_clock = 0;
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tmr_type *tmr_x = RT_NULL;
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struct at32_hwtimer *tmr_device = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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if (state)
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{
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tmr_x = (tmr_type *)timer->parent.user_data;
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tmr_device = (struct at32_hwtimer *)timer;
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/* timer clock enable */
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at32_msp_hwtmr_init(tmr_x);
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/* get timer clock */
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tmr_pclk_get(&pclk1_doubler, &pclk2_doubler);
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crm_clocks_freq_get(&clocks_struct);
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if(
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#if defined (TMR1)
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(tmr_x == TMR1)
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#endif
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#if defined (TMR8)
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|| (tmr_x == TMR8)
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#endif
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#if defined (TMR9)
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|| (tmr_x == TMR9)
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#endif
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#if defined (TMR10)
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|| (tmr_x == TMR10)
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#endif
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#if defined (TMR11)
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|| (tmr_x == TMR11)
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#endif
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)
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{
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tmr_clock = clocks_struct.apb2_freq * pclk2_doubler;
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}
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else
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{
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tmr_clock = clocks_struct.apb1_freq * pclk1_doubler;
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}
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/* set timer clock is 1mhz */
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prescaler_value = (uint32_t)(tmr_clock / 10000) - 1;
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tmr_base_init(tmr_x, 10000 - 1, prescaler_value);
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tmr_clock_source_div_set(tmr_x, TMR_CLOCK_DIV1);
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tmr_repetition_counter_set(tmr_x, 0);
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if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
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{
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tmr_cnt_dir_set(tmr_x, TMR_COUNT_UP);
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}
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else
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{
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tmr_cnt_dir_set(tmr_x, TMR_COUNT_DOWN);
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}
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/* enable the timer global interrupt and clear flag */
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nvic_irq_enable(tmr_device->tmr_irqn, 2, 0);
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tmr_interrupt_enable(tmr_x, TMR_OVF_INT, TRUE);
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tmr_flag_clear(tmr_x, TMR_OVF_INT);
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LOG_D("%s init success", tmr_device->name);
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}
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}
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static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t pr, rt_hwtimer_mode_t opmode)
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{
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rt_err_t result = RT_EOK;
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tmr_type *tmr_x = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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tmr_x = (tmr_type *)timer->parent.user_data;
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/* set tmr_x count */
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tmr_counter_value_set(tmr_x, 0);
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/* set tmr_x period register */
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tmr_period_value_set(tmr_x, pr - 1);
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if (opmode == HWTIMER_MODE_ONESHOT)
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{
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/* set timer to one cycle mode */
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tmr_one_cycle_mode_enable(tmr_x, TRUE);
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}
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else
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{
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/* set timer to period mode */
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tmr_one_cycle_mode_enable(tmr_x, FALSE);
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}
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/* start timer */
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tmr_counter_enable(tmr_x, TRUE);
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return result;
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}
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static void at32_timer_stop(rt_hwtimer_t *timer)
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{
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tmr_type *tmr_x = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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tmr_x = (tmr_type *)timer->parent.user_data;
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/* stop timer */
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tmr_counter_enable(tmr_x, FALSE);
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/* set tmr_x count */
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tmr_counter_value_set(tmr_x, 0);
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}
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static rt_uint32_t at32_timer_counter_get(rt_hwtimer_t *timer)
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{
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tmr_type *tmr_x = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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tmr_x = (tmr_type *)timer->parent.user_data;
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return tmr_counter_value_get(tmr_x);
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}
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static rt_err_t at32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
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{
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crm_clocks_freq_type clocks_struct;
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tmr_type *tmr_x = RT_NULL;
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rt_err_t result = RT_EOK;
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rt_uint32_t pclk1_doubler = 0, pclk2_doubler = 0, tmr_clock = 0;
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RT_ASSERT(timer != RT_NULL);
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RT_ASSERT(arg != RT_NULL);
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tmr_x = (tmr_type *)timer->parent.user_data;
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switch(cmd)
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{
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case HWTIMER_CTRL_FREQ_SET:
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{
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rt_uint32_t freq;
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rt_uint16_t val;
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/* get timer frequence */
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freq = *((rt_uint32_t *)arg);
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/* get timer clock */
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tmr_pclk_get(&pclk1_doubler, &pclk2_doubler);
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crm_clocks_freq_get(&clocks_struct);
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if(
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#if defined (TMR1)
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(tmr_x == TMR1)
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#endif
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#if defined (TMR8)
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|| (tmr_x == TMR8)
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#endif
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#if defined (TMR9)
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|| (tmr_x == TMR9)
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#endif
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#if defined (TMR10)
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|| (tmr_x == TMR10)
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#endif
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#if defined (TMR11)
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|| (tmr_x == TMR11)
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#endif
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)
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{
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tmr_clock = clocks_struct.apb2_freq * pclk2_doubler;
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}
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else
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{
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tmr_clock = clocks_struct.apb1_freq * pclk1_doubler;
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}
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/* set div value */
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val = tmr_clock / freq;
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tmr_div_value_set(tmr_x, val - 1);
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tmr_event_sw_trigger(tmr_x, TMR_OVERFLOW_SWTRIG);
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}
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break;
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default:
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{
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result = -RT_ENOSYS;
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}
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break;
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}
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return result;
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}
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static const struct rt_hwtimer_info _info = TMR_DEV_INFO_CONFIG;
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static const struct rt_hwtimer_ops _ops =
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{
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.init = at32_timer_init,
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.start = at32_timer_start,
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.stop = at32_timer_stop,
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.count_get = at32_timer_counter_get,
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.control = at32_timer_ctrl,
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};
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#ifdef BSP_USING_HWTMR2
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void TMR2_GLOBAL_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if(tmr_flag_get(TMR2, TMR_OVF_FLAG) == SET)
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{
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rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR2_INDEX].tmr_device);
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tmr_flag_clear(TMR2, TMR_OVF_FLAG);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_HWTMR3
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void TMR3_GLOBAL_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if(tmr_flag_get(TMR3, TMR_OVF_FLAG) == SET)
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{
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rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR3_INDEX].tmr_device);
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tmr_flag_clear(TMR3, TMR_OVF_FLAG);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_HWTMR4
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void TMR4_GLOBAL_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if(tmr_flag_get(TMR4, TMR_OVF_FLAG) == SET)
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{
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rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR4_INDEX].tmr_device);
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tmr_flag_clear(TMR4, TMR_OVF_FLAG);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_HWTMR5
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void TMR5_GLOBAL_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if(tmr_flag_get(TMR5, TMR_OVF_FLAG) == SET)
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{
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rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR5_INDEX].tmr_device);
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tmr_flag_clear(TMR5, TMR_OVF_FLAG);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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static int rt_hw_hwtimer_init(void)
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{
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int i = 0;
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int result = RT_EOK;
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for (i = 0; i < sizeof(at32_hwtimer_obj) / sizeof(at32_hwtimer_obj[0]); i++)
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{
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at32_hwtimer_obj[i].tmr_device.info = &_info;
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at32_hwtimer_obj[i].tmr_device.ops = &_ops;
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if (rt_device_hwtimer_register(&at32_hwtimer_obj[i].tmr_device, at32_hwtimer_obj[i].name, at32_hwtimer_obj[i].tmr_x) == RT_EOK)
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{
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LOG_D("%s register success", at32_hwtimer_obj[i].name);
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}
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else
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{
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LOG_E("%s register failed", at32_hwtimer_obj[i].name);
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result = -RT_ERROR;
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}
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}
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
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#endif /* BSP_USING_HWTIMER */
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