521 lines
13 KiB
C
521 lines
13 KiB
C
/*
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* Copyright (c) 2020-2022, CQ 100ask Development Team
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*
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* Change Logs:
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* Date Author Notes
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* 2022-05-29 Alen first version
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*/
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#include "drv_gpio.h"
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#ifdef RT_USING_PIN
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#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
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#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
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#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
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#define PIN_STPORT(pin) ((GPIO_Type *)(GPIOA_BASE + (0x400u * PIN_PORT(pin))))
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#define PIN_STPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
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#if defined(GPIOF)
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#define __MM32_PORT_MAX 6u
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#elif defined(GPIOE)
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#define __MM32_PORT_MAX 5u
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#elif defined(GPIOD)
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#define __MM32_PORT_MAX 4u
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#elif defined(GPIOC)
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#define __MM32_PORT_MAX 3u
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#elif defined(GPIOB)
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#define __MM32_PORT_MAX 2u
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#elif defined(GPIOA)
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#define __MM32_PORT_MAX 1u
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#else
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#define __MM32_PORT_MAX 0u
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#error Unsupported MM32 GPIO peripheral.
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#endif
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#define PIN_STPORT_MAX __MM32_PORT_MAX
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#define GET_EXTI_PORT(PORT)
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static const struct pin_irq_map pin_irq_map[] =
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{
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{GPIO_PIN_0, EXTI0_IRQn, EXTI_LINE_0, SYSCFG_EXTILine_0},
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{GPIO_PIN_1, EXTI1_IRQn, EXTI_LINE_1, SYSCFG_EXTILine_1},
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{GPIO_PIN_2, EXTI2_IRQn, EXTI_LINE_2, SYSCFG_EXTILine_2},
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{GPIO_PIN_3, EXTI3_IRQn, EXTI_LINE_3, SYSCFG_EXTILine_3},
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{GPIO_PIN_4, EXTI4_IRQn, EXTI_LINE_4, SYSCFG_EXTILine_4},
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{GPIO_PIN_5, EXTI9_5_IRQn, EXTI_LINE_5,SYSCFG_EXTILine_5},
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{GPIO_PIN_6, EXTI9_5_IRQn, EXTI_LINE_6, SYSCFG_EXTILine_6},
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{GPIO_PIN_7, EXTI9_5_IRQn, EXTI_LINE_7, SYSCFG_EXTILine_7},
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{GPIO_PIN_8, EXTI9_5_IRQn, EXTI_LINE_8, SYSCFG_EXTILine_8},
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{GPIO_PIN_9, EXTI9_5_IRQn, EXTI_LINE_9, SYSCFG_EXTILine_9},
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{GPIO_PIN_10, EXTI15_10_IRQn, EXTI_LINE_10, SYSCFG_EXTILine_10},
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{GPIO_PIN_11, EXTI15_10_IRQn, EXTI_LINE_11, SYSCFG_EXTILine_11},
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{GPIO_PIN_12, EXTI15_10_IRQn, EXTI_LINE_12, SYSCFG_EXTILine_12},
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{GPIO_PIN_13, EXTI15_10_IRQn, EXTI_LINE_13, SYSCFG_EXTILine_13},
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{GPIO_PIN_14, EXTI15_10_IRQn, EXTI_LINE_14, SYSCFG_EXTILine_14},
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{GPIO_PIN_15, EXTI15_10_IRQn, EXTI_LINE_15, SYSCFG_EXTILine_15},
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};
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static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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static uint32_t pin_irq_enable_mask = 0;
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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static rt_base_t mm32_pin_get(const char *name)
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{
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rt_base_t pin = 0;
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int hw_port_num, hw_pin_num = 0;
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int i, name_len;
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name_len = rt_strlen(name);
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if ((name_len < 4) || (name_len >= 6))
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{
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return -RT_EINVAL;
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}
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if ((name[0] != 'P') || (name[2] != '.'))
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{
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return -RT_EINVAL;
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}
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if ((name[1] >= 'A') && (name[1] <= 'F'))
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{
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hw_port_num = (int)(name[1] - 'A');
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}
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else
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{
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return -RT_EINVAL;
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}
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for (i = 3; i < name_len; i++)
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{
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hw_pin_num *= 10;
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hw_pin_num += name[i] - '0';
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}
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pin = PIN_NUM(hw_port_num, hw_pin_num);
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return pin;
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}
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static void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
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{
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GPIO_Type *gpio_port;
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uint16_t gpio_pin;
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if (PIN_PORT(pin) < PIN_STPORT_MAX)
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{
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gpio_port = PIN_STPORT(pin);
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gpio_pin = PIN_STPIN(pin);
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GPIO_WriteBit(gpio_port, gpio_pin, (rt_uint16_t)value);
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}
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}
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static rt_ssize_t mm32_pin_read(rt_device_t dev, rt_base_t pin)
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{
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GPIO_Type *gpio_port;
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uint16_t gpio_pin;
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rt_ssize_t value = PIN_LOW;
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if (PIN_PORT(pin) < PIN_STPORT_MAX)
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{
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gpio_port = PIN_STPORT(pin);
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gpio_pin = PIN_STPIN(pin);
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value = GPIO_ReadInDataBit(gpio_port, gpio_pin);
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}
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else
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{
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return -RT_EINVAL;
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}
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return value;
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}
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static void mm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
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{
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GPIO_Init_Type GPIO_InitStruct;
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if (PIN_PORT(pin) >= PIN_STPORT_MAX)
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{
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return;
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}
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/* Configure GPIO_InitStructure */
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GPIO_InitStruct.Pins = PIN_STPIN(pin);
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GPIO_InitStruct.PinMode = GPIO_PinMode_Out_PushPull;
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GPIO_InitStruct.Speed = GPIO_Speed_50MHz;
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if (mode == PIN_MODE_OUTPUT)
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{
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/* output setting */
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GPIO_InitStruct.PinMode = GPIO_PinMode_Out_PushPull;
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}
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else if (mode == PIN_MODE_INPUT)
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{
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/* input setting: not pull. */
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GPIO_InitStruct.PinMode = GPIO_PinMode_In_Floating;
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}
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else if (mode == PIN_MODE_INPUT_PULLUP)
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{
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/* input setting: pull up. */
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GPIO_InitStruct.PinMode = GPIO_PinMode_In_PullUp;
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}
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else if (mode == PIN_MODE_INPUT_PULLDOWN)
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{
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/* input setting: pull down. */
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GPIO_InitStruct.PinMode = GPIO_PinMode_In_PullDown;
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}
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else if (mode == PIN_MODE_OUTPUT_OD)
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{
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/* output setting: od. */
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GPIO_InitStruct.PinMode = GPIO_PinMode_Out_OpenDrain;
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}
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GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct);
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}
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rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
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{
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rt_uint8_t i;
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for (i = 0; i < 32; i++)
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{
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if ((0x01 << i) == bit)
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{
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return i;
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}
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}
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return -1;
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}
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rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
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{
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rt_int32_t mapindex = bit2bitno(pinbit);
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if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_NULL;
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}
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return &pin_irq_map[mapindex];
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};
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static rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
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rt_uint8_t mode, void (*hdr)(void *args), void *args)
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{
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rt_base_t level;
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rt_int32_t irqindex = -1;
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if (PIN_PORT(pin) >= PIN_STPORT_MAX)
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{
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return -RT_ENOSYS;
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}
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irqindex = bit2bitno(PIN_STPIN(pin));
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return -RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == pin &&
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pin_irq_hdr_tab[irqindex].hdr == hdr &&
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pin_irq_hdr_tab[irqindex].mode == mode &&
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pin_irq_hdr_tab[irqindex].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_tab[irqindex].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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return -RT_EBUSY;
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}
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pin_irq_hdr_tab[irqindex].pin = pin;
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pin_irq_hdr_tab[irqindex].hdr = hdr;
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pin_irq_hdr_tab[irqindex].mode = mode;
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pin_irq_hdr_tab[irqindex].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t mm32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
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{
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rt_base_t level;
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rt_int32_t irqindex = -1;
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if (PIN_PORT(pin) >= PIN_STPORT_MAX)
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{
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return -RT_ENOSYS;
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}
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irqindex = bit2bitno(PIN_STPIN(pin));
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return -RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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pin_irq_hdr_tab[irqindex].pin = -1;
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pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
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pin_irq_hdr_tab[irqindex].mode = 0;
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pin_irq_hdr_tab[irqindex].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t mm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
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rt_uint8_t enabled)
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{
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const struct pin_irq_map *irqmap;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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GPIO_Init_Type GPIO_InitStruct;
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if (PIN_PORT(pin) >= PIN_STPORT_MAX)
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{
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return -RT_ENOSYS;
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}
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if (enabled == PIN_IRQ_ENABLE)
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{
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irqindex = bit2bitno(PIN_STPIN(pin));
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return -RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return -RT_ENOSYS;
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}
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irqmap = &pin_irq_map[irqindex];
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/* Configure GPIO_InitStructure */
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GPIO_InitStruct.Pins = PIN_STPIN(pin);
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GPIO_InitStruct.Speed = GPIO_Speed_50MHz;
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GPIO_InitStruct.PinMode = GPIO_PinMode_In_PullUp;
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GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct);
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SYSCFG_SetExtIntMux(SYSCFG_EXTIPort_GPIOA + (0 == (rt_uint32_t)PIN_PORT(pin)?0: PIN_PORT(pin)/GPIOB_BASE), irqmap->syscfg_extiline);
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switch (pin_irq_hdr_tab[irqindex].mode)
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{
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case PIN_IRQ_MODE_RISING:
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EXTI_SetTriggerIn(EXTI, irqmap->extiline, EXTI_TriggerIn_RisingEdge);
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break;
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case PIN_IRQ_MODE_FALLING:
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EXTI_SetTriggerIn(EXTI, irqmap->extiline, EXTI_TriggerIn_FallingEdge);
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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EXTI_SetTriggerIn(EXTI, irqmap->extiline, EXTI_TriggerIn_BothEdges);
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break;
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}
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EXTI_EnableLineInterrupt(EXTI, irqmap->extiline, true);
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NVIC_SetPriority(irqmap->irqno, NVIC_EncodePriority(4, 5, 0));
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NVIC_EnableIRQ(irqmap->irqno);
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pin_irq_enable_mask |= irqmap->pinbit;
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rt_hw_interrupt_enable(level);
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}
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else if (enabled == PIN_IRQ_DISABLE)
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{
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irqmap = get_pin_irq_map(PIN_STPIN(pin));
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if (irqmap == RT_NULL)
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{
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return -RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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pin_irq_enable_mask &= ~irqmap->pinbit;
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if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9))
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{
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if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9)))
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{
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NVIC_DisableIRQ(irqmap->irqno);
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}
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}
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else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15))
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{
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if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)))
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{
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NVIC_DisableIRQ(irqmap->irqno);
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}
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}
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else
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{
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NVIC_DisableIRQ(irqmap->irqno);
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}
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rt_hw_interrupt_enable(level);
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}
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else
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{
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return -RT_ENOSYS;
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}
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return RT_EOK;
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}
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const static struct rt_pin_ops _mm32_pin_ops =
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{
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mm32_pin_mode,
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mm32_pin_write,
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mm32_pin_read,
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mm32_pin_attach_irq,
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mm32_pin_dettach_irq,
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mm32_pin_irq_enable,
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mm32_pin_get,
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};
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rt_inline void pin_irq_hdr(int irqno)
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{
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if (pin_irq_hdr_tab[irqno].hdr)
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{
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pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
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}
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}
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void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
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{
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pin_irq_hdr(bit2bitno(GPIO_Pin));
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}
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#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
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#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
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void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
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{
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/* EXTI line interrupt detected */
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if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
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{
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__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
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HAL_GPIO_EXTI_Callback(GPIO_Pin);
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}
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}
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void EXTI0_IRQHandler(void)
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{
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rt_interrupt_enter();
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
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rt_interrupt_leave();
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}
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void EXTI1_IRQHandler(void)
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{
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rt_interrupt_enter();
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
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rt_interrupt_leave();
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}
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void EXTI2_IRQHandler(void)
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{
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rt_interrupt_enter();
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
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rt_interrupt_leave();
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}
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void EXTI3_IRQHandler(void)
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{
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rt_interrupt_enter();
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
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rt_interrupt_leave();
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}
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void EXTI4_IRQHandler(void)
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{
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rt_interrupt_enter();
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
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rt_interrupt_leave();
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}
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void EXTI9_5_IRQHandler(void)
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{
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rt_interrupt_enter();
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
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rt_interrupt_leave();
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}
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void EXTI15_10_IRQHandler(void)
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{
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rt_interrupt_enter();
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
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rt_interrupt_leave();
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}
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int rt_hw_pin_init(void)
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{
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#if defined(RCC_AHB1_PERIPH_GPIOA)
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RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOA, true);
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#endif
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#if defined(RCC_AHB1_PERIPH_GPIOB)
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RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOB, true);
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#endif
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#if defined(RCC_AHB1_PERIPH_GPIOC)
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RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOC, true);
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#endif
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#if defined(RCC_AHB1_PERIPH_GPIOD)
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RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOD, true);
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#endif
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#if defined(RCC_AHB1_PERIPH_GPIOE)
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RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOE, true);
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#endif
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#if defined(RCC_AHB1_PERIPH_GPIOF)
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RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOF, true);
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#endif
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#if defined(RCC_APB2_PERIPH_SYSCFG)
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RCC_EnableAPB2Periphs(RCC_APB2_PERIPH_SYSCFG, true);
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#endif
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return rt_device_pin_register("pin", &_mm32_pin_ops, RT_NULL);
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}
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#endif /* RT_USING_PIN */
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