239 lines
13 KiB
C
239 lines
13 KiB
C
/*!
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\file gd32f4xx_dci.h
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\brief definitions for the DCI
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\version 2016-08-15, V1.0.0, firmware for GD32F4xx
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\version 2018-12-12, V2.0.0, firmware for GD32F4xx
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\version 2020-09-30, V2.1.0, firmware for GD32F4xx
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*/
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/*
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Copyright (c) 2020, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F4XX_DCI_H
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#define GD32F4XX_DCI_H
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#include "gd32f4xx.h"
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/* DCI definitions */
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#define DCI DCI_BASE
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/* registers definitions */
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#define DCI_CTL REG32(DCI + 0x00U) /*!< DCI control register */
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#define DCI_STAT0 REG32(DCI + 0x04U) /*!< DCI status register 0 */
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#define DCI_STAT1 REG32(DCI + 0x08U) /*!< DCI status register 1 */
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#define DCI_INTEN REG32(DCI + 0x0CU) /*!< DCI interrupt enable register */
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#define DCI_INTF REG32(DCI + 0x10U) /*!< DCI interrupt flag register */
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#define DCI_INTC REG32(DCI + 0x14U) /*!< DCI interrupt clear register */
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#define DCI_SC REG32(DCI + 0x18U) /*!< DCI synchronization codes register */
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#define DCI_SCUMSK REG32(DCI + 0x1CU) /*!< DCI synchronization codes unmask register */
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#define DCI_CWSPOS REG32(DCI + 0x20U) /*!< DCI cropping window start position register */
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#define DCI_CWSZ REG32(DCI + 0x24U) /*!< DCI cropping window size register */
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#define DCI_DATA REG32(DCI + 0x28U) /*!< DCI data register */
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/* bits definitions */
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/* DCI_CTL */
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#define DCI_CTL_CAP BIT(0) /*!< capture enable */
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#define DCI_CTL_SNAP BIT(1) /*!< snapshot mode */
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#define DCI_CTL_WDEN BIT(2) /*!< window enable */
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#define DCI_CTL_JM BIT(3) /*!< JPEG mode */
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#define DCI_CTL_ESM BIT(4) /*!< embedded synchronous mode */
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#define DCI_CTL_CKS BIT(5) /*!< clock polarity selection */
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#define DCI_CTL_HPS BIT(6) /*!< horizontal polarity selection */
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#define DCI_CTL_VPS BIT(7) /*!< vertical polarity selection */
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#define DCI_CTL_FR BITS(8,9) /*!< frame rate */
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#define DCI_CTL_DCIF BITS(10,11) /*!< digital camera interface format */
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#define DCI_CTL_DCIEN BIT(14) /*!< DCI enable */
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/* DCI_STAT0 */
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#define DCI_STAT0_HS BIT(0) /*!< HS line status */
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#define DCI_STAT0_VS BIT(1) /*!< VS line status */
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#define DCI_STAT0_FV BIT(2) /*!< FIFO valid */
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/* DCI_STAT1 */
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#define DCI_STAT1_EFF BIT(0) /*!< end of frame flag */
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#define DCI_STAT1_OVRF BIT(1) /*!< FIFO overrun flag */
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#define DCI_STAT1_ESEF BIT(2) /*!< embedded synchronous error flag */
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#define DCI_STAT1_VSF BIT(3) /*!< vsync flag */
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#define DCI_STAT1_ELF BIT(4) /*!< end of line flag */
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/* DCI_INTEN */
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#define DCI_INTEN_EFIE BIT(0) /*!< end of frame interrupt enable */
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#define DCI_INTEN_OVRIE BIT(1) /*!< FIFO overrun interrupt enable */
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#define DCI_INTEN_ESEIE BIT(2) /*!< embedded synchronous error interrupt enable */
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#define DCI_INTEN_VSIE BIT(3) /*!< vsync interrupt enable */
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#define DCI_INTEN_ELIE BIT(4) /*!< end of line interrupt enable */
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/* DCI_INTF */
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#define DCI_INTF_EFIF BIT(0) /*!< end of frame interrupt flag */
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#define DCI_INTF_OVRIF BIT(1) /*!< FIFO overrun interrupt flag */
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#define DCI_INTF_ESEIF BIT(2) /*!< embedded synchronous error interrupt flag */
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#define DCI_INTF_VSIF BIT(3) /*!< vsync interrupt flag */
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#define DCI_INTF_ELIF BIT(4) /*!< end of line interrupt flag */
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/* DCI_INTC */
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#define DCI_INTC_EFFC BIT(0) /*!< clear end of frame flag */
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#define DCI_INTC_OVRFC BIT(1) /*!< clear FIFO overrun flag */
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#define DCI_INTC_ESEFC BIT(2) /*!< clear embedded synchronous error flag */
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#define DCI_INTC_VSFC BIT(3) /*!< vsync flag clear */
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#define DCI_INTC_ELFC BIT(4) /*!< end of line flag clear */
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/* DCI_SC */
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#define DCI_SC_FS BITS(0,7) /*!< frame start code in embedded synchronous mode */
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#define DCI_SC_LS BITS(8,15) /*!< line start code in embedded synchronous mode */
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#define DCI_SC_LE BITS(16,23) /*!< line end code in embedded synchronous mode */
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#define DCI_SC_FE BITS(24,31) /*!< frame end code in embedded synchronous mode */
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/* DCI_SCUNMSK */
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#define DCI_SCUMSK_FSM BITS(0,7) /*!< frame start code unmask bits in embedded synchronous mode */
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#define DCI_SCUMSK_LSM BITS(8,15) /*!< line start code unmask bits in embedded synchronous mode */
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#define DCI_SCUMSK_LEM BITS(16,23) /*!< line end code unmask bits in embedded synchronous mode */
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#define DCI_SCUMSK_FEM BITS(24,31) /*!< frame end code unmask bits in embedded synchronous mode */
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/* DCI_CWSPOS */
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#define DCI_CWSPOS_WHSP BITS(0,13) /*!< window horizontal start position */
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#define DCI_CWSPOS_WVSP BITS(16,28) /*!< window vertical start position */
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/* DCI_CWSZ */
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#define DCI_CWSZ_WHSZ BITS(0,13) /*!< window horizontal size */
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#define DCI_CWSZ_WVSZ BITS(16,29) /*!< window vertical size */
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/* constants definitions */
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/* DCI parameter structure definitions */
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typedef struct
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{
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uint32_t capture_mode; /*!< DCI capture mode: continuous or snapshot */
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uint32_t clock_polarity; /*!< clock polarity selection */
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uint32_t hsync_polarity; /*!< horizontal polarity selection */
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uint32_t vsync_polarity; /*!< vertical polarity selection */
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uint32_t frame_rate; /*!< frame capture rate */
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uint32_t interface_format; /*!< digital camera interface format */
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}dci_parameter_struct;
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#define DCI_CAPTURE_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< continuous capture mode */
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#define DCI_CAPTURE_MODE_SNAPSHOT DCI_CTL_SNAP /*!< snapshot capture mode */
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#define DCI_CK_POLARITY_FALLING ((uint32_t)0x00000000U) /*!< capture at falling edge */
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#define DCI_CK_POLARITY_RISING DCI_CTL_CKS /*!< capture at rising edge */
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#define DCI_HSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */
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#define DCI_HSYNC_POLARITY_HIGH DCI_CTL_HPS /*!< high level during blanking period */
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#define DCI_VSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */
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#define DCI_VSYNC_POLARITY_HIGH DCI_CTL_VPS /*!< high level during blanking period*/
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#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U))
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#define DCI_FRAME_RATE_ALL CTL_FR(0) /*!< capture all frames */
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#define DCI_FRAME_RATE_1_2 CTL_FR(1) /*!< capture one in 2 frames */
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#define DCI_FRAME_RATE_1_4 CTL_FR(2) /*!< capture one in 4 frames */
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#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U))
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#define DCI_INTERFACE_FORMAT_8BITS CTL_DCIF(0) /*!< 8-bit data on every pixel clock */
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#define DCI_INTERFACE_FORMAT_10BITS CTL_DCIF(1) /*!< 10-bit data on every pixel clock */
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#define DCI_INTERFACE_FORMAT_12BITS CTL_DCIF(2) /*!< 12-bit data on every pixel clock */
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#define DCI_INTERFACE_FORMAT_14BITS CTL_DCIF(3) /*!< 14-bit data on every pixel clock */
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/* DCI interrupt constants definitions */
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#define DCI_INT_EF BIT(0) /*!< end of frame interrupt */
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#define DCI_INT_OVR BIT(1) /*!< FIFO overrun interrupt */
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#define DCI_INT_ESE BIT(2) /*!< embedded synchronous error interrupt */
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#define DCI_INT_VSYNC BIT(3) /*!< vsync interrupt */
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#define DCI_INT_EL BIT(4) /*!< end of line interrupt */
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/* DCI interrupt flag definitions */
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#define DCI_INT_FLAG_EF BIT(0) /*!< end of frame interrupt flag */
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#define DCI_INT_FLAG_OVR BIT(1) /*!< FIFO overrun interrupt flag */
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#define DCI_INT_FLAG_ESE BIT(2) /*!< embedded synchronous error interrupt flag */
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#define DCI_INT_FLAG_VSYNC BIT(3) /*!< vsync interrupt flag */
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#define DCI_INT_FLAG_EL BIT(4) /*!< end of line interrupt flag */
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/* DCI flag definitions */
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#define DCI_FLAG_HS DCI_STAT0_HS /*!< HS line status */
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#define DCI_FLAG_VS DCI_STAT0_VS /*!< VS line status */
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#define DCI_FLAG_FV DCI_STAT0_FV /*!< FIFO valid */
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#define DCI_FLAG_EF (DCI_STAT1_EFF | BIT(31)) /*!< end of frame flag */
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#define DCI_FLAG_OVR (DCI_STAT1_OVRF | BIT(31)) /*!< FIFO overrun flag */
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#define DCI_FLAG_ESE (DCI_STAT1_ESEF | BIT(31)) /*!< embedded synchronous error flag */
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#define DCI_FLAG_VSYNC (DCI_STAT1_VSF | BIT(31)) /*!< vsync flag */
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#define DCI_FLAG_EL (DCI_STAT1_ELF | BIT(31)) /*!< end of line flag */
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/* function declarations */
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/* initialization functions */
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/* DCI deinit */
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void dci_deinit(void);
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/* initialize DCI registers */
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void dci_init(dci_parameter_struct* dci_struct);
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/* enable DCI function */
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void dci_enable(void);
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/* disable DCI function */
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void dci_disable(void);
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/* enable DCI capture */
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void dci_capture_enable(void);
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/* disable DCI capture */
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void dci_capture_disable(void);
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/* enable DCI jpeg mode */
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void dci_jpeg_enable(void);
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/* disable DCI jpeg mode */
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void dci_jpeg_disable(void);
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/* function configuration */
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/* enable cropping window function */
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void dci_crop_window_enable(void);
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/* disable cropping window function */
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void dci_crop_window_disable(void);
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/* configure DCI cropping window */
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void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height);
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/* enable embedded synchronous mode */
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void dci_embedded_sync_enable(void);
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/* disable embedded synchronous mode */
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void dci_embedded_sync_disable(void);
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/* configure synchronous codes in embedded synchronous mode */
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void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end);
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/* configure synchronous codes unmask in embedded synchronous mode */
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void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end);
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/* read DCI data register */
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uint32_t dci_data_read(void);
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/* interrupt & flag functions */
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/* get specified flag */
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FlagStatus dci_flag_get(uint32_t flag);
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/* enable specified DCI interrupt */
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void dci_interrupt_enable(uint32_t interrupt);
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/* disable specified DCI interrupt */
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void dci_interrupt_disable(uint32_t interrupt);
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/* get specified interrupt flag */
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FlagStatus dci_interrupt_flag_get(uint32_t int_flag);
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/* clear specified interrupt flag */
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void dci_interrupt_flag_clear(uint32_t int_flag);
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#endif /* GD32F4XX_DCI_H */
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