604 lines
14 KiB
C
604 lines
14 KiB
C
/*
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* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Change Logs:
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* Date Author Notes
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* 2019-01-23 wangyq the first version
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* 2019-11-01 wangyq update libraries
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* 2021-04-20 liuhy the second version
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*/
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#include "board.h"
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#include "drv_gpio.h"
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/*管脚映射在 es_conf_info_map.h 的 pins[] 中*/
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#ifdef RT_USING_PIN
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struct pin_irq_map
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{
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rt_uint16_t pinbit;
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IRQn_Type irqno;
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};
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static const struct pin_irq_map pin_irq_map[] =
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{
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{GPIO_PIN_0, EXTI0_3_IRQn},
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{GPIO_PIN_1, EXTI0_3_IRQn},
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{GPIO_PIN_2, EXTI0_3_IRQn},
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{GPIO_PIN_3, EXTI0_3_IRQn},
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{GPIO_PIN_4, EXTI4_7_IRQn},
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{GPIO_PIN_5, EXTI4_7_IRQn},
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{GPIO_PIN_6, EXTI4_7_IRQn},
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{GPIO_PIN_7, EXTI4_7_IRQn},
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{GPIO_PIN_8, EXTI8_11_IRQn},
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{GPIO_PIN_9, EXTI8_11_IRQn},
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{GPIO_PIN_10, EXTI8_11_IRQn},
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{GPIO_PIN_11, EXTI8_11_IRQn},
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{GPIO_PIN_12, EXTI12_15_IRQn},
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{GPIO_PIN_13, EXTI12_15_IRQn},
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{GPIO_PIN_14, EXTI12_15_IRQn},
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{GPIO_PIN_15, EXTI12_15_IRQn},
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};
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struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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};
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#ifdef ES_CONF_EXTI_IRQ_0
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rt_weak void irq_pin0_callback(void* arg)
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{
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rt_kprintf("\r\nEXTI 0\r\n");
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}
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#endif
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#ifdef ES_CONF_EXTI_IRQ_1
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rt_weak void irq_pin1_callback(void* arg)
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{
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rt_kprintf("\r\nEXTI 1\r\n");
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}
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#endif
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#ifdef ES_CONF_EXTI_IRQ_2
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rt_weak void irq_pin2_callback(void* arg)
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{
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rt_kprintf("\r\nEXTI 2\r\n");
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}
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#endif
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#ifdef ES_CONF_EXTI_IRQ_3
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rt_weak void irq_pin3_callback(void* arg)
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{
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rt_kprintf("\r\nEXTI 3\r\n");
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}
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#endif
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#ifdef ES_CONF_EXTI_IRQ_4
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rt_weak void irq_pin4_callback(void* arg)
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{
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rt_kprintf("\r\nEXTI 4\r\n");
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}
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#endif
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#ifdef ES_CONF_EXTI_IRQ_5
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rt_weak void irq_pin5_callback(void* arg)
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{
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rt_kprintf("\r\nEXTI 5\r\n");
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}
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#endif
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#ifdef ES_CONF_EXTI_IRQ_6
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rt_weak void irq_pin6_callback(void* arg)
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{
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rt_kprintf("\r\nEXTI 6\r\n");
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}
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#endif
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#ifdef ES_CONF_EXTI_IRQ_7
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rt_weak void irq_pin7_callback(void* arg)
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{
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rt_kprintf("\r\nEXTI 7\r\n");
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}
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#endif
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#ifdef ES_CONF_EXTI_IRQ_8
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rt_weak void irq_pin8_callback(void* arg)
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{
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rt_kprintf("\r\nEXTI 8\r\n");
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}
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#endif
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#ifdef ES_CONF_EXTI_IRQ_9
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rt_weak void irq_pin9_callback(void* arg)
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{
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rt_kprintf("\r\nEXTI 9\r\n");
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}
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#endif
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#ifdef ES_CONF_EXTI_IRQ_10
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rt_weak void irq_pin10_callback(void* arg)
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{
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rt_kprintf("\r\nEXTI 10\r\n");
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}
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#endif
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#ifdef ES_CONF_EXTI_IRQ_11
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rt_weak void irq_pin11_callback(void* arg)
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{
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rt_kprintf("\r\nEXTI 11\r\n");
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}
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#endif
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#ifdef ES_CONF_EXTI_IRQ_12
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rt_weak void irq_pin12_callback(void* arg)
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{
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rt_kprintf("\r\nEXTI 12\r\n");
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}
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#endif
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#ifdef ES_CONF_EXTI_IRQ_13
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rt_weak void irq_pin13_callback(void* arg)
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{
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rt_kprintf("\r\nEXTI 13\r\n");
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}
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#endif
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#ifdef ES_CONF_EXTI_IRQ_14
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rt_weak void irq_pin14_callback(void* arg)
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{
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rt_kprintf("\r\nEXTI 14\r\n");
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}
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#endif
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#ifdef ES_CONF_EXTI_IRQ_15
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rt_weak void irq_pin15_callback(void* arg)
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{
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rt_kprintf("\r\nEXTI 15\r\n");
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}
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#endif
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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const struct pin_index *get_pin(uint8_t pin)
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{
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const struct pin_index *index;
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if (pin < ITEM_NUM(pins))
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{
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index = &pins[pin];
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if (index->index == -1)
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index = RT_NULL;
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}
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else
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{
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index = RT_NULL;
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}
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return index;
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};
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void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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const struct pin_index *index;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return;
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}
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ald_gpio_write_pin(index->gpio, index->pin, value);
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}
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int es32f0_pin_read(rt_device_t dev, rt_base_t pin)
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{
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int value;
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const struct pin_index *index;
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value = PIN_LOW;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return value;
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}
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value = ald_gpio_read_pin(index->gpio, index->pin);
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return value;
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}
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void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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const struct pin_index *index;
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gpio_init_t gpio_initstruct;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return;
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}
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/* Configure GPIO_InitStructure */
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gpio_initstruct.mode = GPIO_MODE_OUTPUT;
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gpio_initstruct.func = GPIO_FUNC_1;
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gpio_initstruct.odrv = GPIO_OUT_DRIVE_NORMAL;
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gpio_initstruct.type = GPIO_TYPE_CMOS;
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gpio_initstruct.pupd = GPIO_FLOATING;
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gpio_initstruct.odos = GPIO_PUSH_PULL;
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if (mode == PIN_MODE_OUTPUT)
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{
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/* output setting */
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gpio_initstruct.mode = GPIO_MODE_OUTPUT;
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gpio_initstruct.pupd = GPIO_FLOATING;
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}
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else if (mode == PIN_MODE_INPUT)
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{
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/* input setting: not pull. */
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gpio_initstruct.mode = GPIO_MODE_INPUT;
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gpio_initstruct.pupd = GPIO_FLOATING;
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}
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else if (mode == PIN_MODE_INPUT_PULLUP)
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{
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/* input setting: pull up. */
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gpio_initstruct.mode = GPIO_MODE_INPUT;
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gpio_initstruct.pupd = GPIO_PUSH_UP;
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}
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else if (mode == PIN_MODE_INPUT_PULLDOWN)
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{
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/* input setting: pull down. */
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gpio_initstruct.mode = GPIO_MODE_INPUT;
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gpio_initstruct.pupd = GPIO_PUSH_DOWN;
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}
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else if (mode == PIN_MODE_OUTPUT_OD)
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{
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/* output setting: od. */
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gpio_initstruct.mode = GPIO_MODE_OUTPUT;
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gpio_initstruct.pupd = GPIO_FLOATING;
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gpio_initstruct.odos = GPIO_OPEN_DRAIN;
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}
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ald_gpio_init(index->gpio, index->pin, &gpio_initstruct);
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}
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rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
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{
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uint8_t map_index = 0U;
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while(gpio_pin >> (++map_index))
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{
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}
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map_index--;
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if (map_index >= ITEM_NUM(pin_irq_map))
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{
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return RT_NULL;
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}
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return &pin_irq_map[map_index];
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};
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rt_err_t es32f0_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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const struct pin_index *index;
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rt_base_t level;
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rt_int32_t irqindex;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return -RT_ENOSYS;
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}
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/* pin no. convert to dec no. */
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for (irqindex = 0; irqindex < 16; irqindex++)
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{
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if ((0x01 << irqindex) == index->pin)
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{
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break;
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}
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}
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return -RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == pin &&
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pin_irq_hdr_tab[irqindex].hdr == hdr &&
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pin_irq_hdr_tab[irqindex].mode == mode &&
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pin_irq_hdr_tab[irqindex].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_tab[irqindex].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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return -RT_EBUSY;
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}
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pin_irq_hdr_tab[irqindex].pin = pin;
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pin_irq_hdr_tab[irqindex].hdr = hdr;
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pin_irq_hdr_tab[irqindex].mode = mode;
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pin_irq_hdr_tab[irqindex].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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rt_err_t es32f0_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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{
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const struct pin_index *index;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return -RT_ENOSYS;
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}
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irqindex = index->pin & 0x00FF;
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return -RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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pin_irq_hdr_tab[irqindex].pin = -1;
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pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
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pin_irq_hdr_tab[irqindex].mode = 0;
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pin_irq_hdr_tab[irqindex].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin,
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rt_uint32_t enabled)
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{
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const struct pin_index *index;
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const struct pin_irq_map *irqmap;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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/* Configure GPIO_InitStructure & EXTI_InitStructure */
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gpio_init_t gpio_initstruct;
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exti_init_t exti_initstruct;
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exti_initstruct.filter = DISABLE;
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exti_initstruct.cks = EXTI_FILTER_CLOCK_10K;
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exti_initstruct.filter_time = 0x0;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return -RT_ENOSYS;
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}
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if (enabled == PIN_IRQ_ENABLE)
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{
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/* pin no. convert to dec no. */
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for (irqindex = 0; irqindex < 16; irqindex++)
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{
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if ((0x01 << irqindex) == index->pin)
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{
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break;
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}
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}
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return -RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return -RT_ENOSYS;
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}
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irqmap = &pin_irq_map[irqindex];
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ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct);
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/* Configure GPIO_InitStructure */
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gpio_initstruct.mode = GPIO_MODE_INPUT;
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gpio_initstruct.func = GPIO_FUNC_1;
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switch (pin_irq_hdr_tab[irqindex].mode)
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{
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case PIN_IRQ_MODE_RISING:
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gpio_initstruct.pupd = GPIO_PUSH_DOWN;
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ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE);
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break;
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case PIN_IRQ_MODE_FALLING:
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gpio_initstruct.pupd = GPIO_PUSH_UP;
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ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE);
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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gpio_initstruct.pupd = GPIO_FLOATING;
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ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE);
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break;
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}
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ald_gpio_init(index->gpio, index->pin, &gpio_initstruct);
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NVIC_EnableIRQ(irqmap->irqno);
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rt_hw_interrupt_enable(level);
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}
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else if (enabled == PIN_IRQ_DISABLE)
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{
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irqmap = get_pin_irq_map(index->pin);
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if (irqmap == RT_NULL)
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{
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return -RT_ENOSYS;
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}
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NVIC_DisableIRQ(irqmap->irqno);
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}
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else
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{
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return -RT_ENOSYS;
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}
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return RT_EOK;
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}
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const static struct rt_pin_ops _es32f0_pin_ops =
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{
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es32f0_pin_mode,
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es32f0_pin_write,
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es32f0_pin_read,
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es32f0_pin_attach_irq,
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es32f0_pin_detach_irq,
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es32f0_pin_irq_enable,
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/*RT_NULL,*/
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};
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rt_inline void pin_irq_hdr(uint16_t GPIO_Pin)
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{
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uint16_t irqno;
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/* pin no. convert to dec no. */
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for (irqno = 0; irqno < 16; irqno++)
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{
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if ((0x01 << irqno) == GPIO_Pin)
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{
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break;
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}
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}
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if (irqno == 16)
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return;
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if (pin_irq_hdr_tab[irqno].hdr)
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{
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pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
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}
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}
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void GPIO_EXTI_Callback(uint16_t GPIO_Pin)
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{
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if (ald_gpio_exti_get_flag_status(GPIO_Pin) != RESET)
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{
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ald_gpio_exti_clear_flag_status(GPIO_Pin);
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pin_irq_hdr(GPIO_Pin);
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}
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}
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void EXTI0_3_Handler(void)
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{
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rt_interrupt_enter();
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GPIO_EXTI_Callback(GPIO_PIN_0);
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GPIO_EXTI_Callback(GPIO_PIN_1);
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GPIO_EXTI_Callback(GPIO_PIN_2);
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GPIO_EXTI_Callback(GPIO_PIN_3);
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rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI4_7_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
GPIO_EXTI_Callback(GPIO_PIN_4);
|
|
GPIO_EXTI_Callback(GPIO_PIN_5);
|
|
GPIO_EXTI_Callback(GPIO_PIN_6);
|
|
GPIO_EXTI_Callback(GPIO_PIN_7);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI8_11_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
GPIO_EXTI_Callback(GPIO_PIN_8);
|
|
GPIO_EXTI_Callback(GPIO_PIN_9);
|
|
GPIO_EXTI_Callback(GPIO_PIN_10);
|
|
GPIO_EXTI_Callback(GPIO_PIN_11);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI12_15_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
GPIO_EXTI_Callback(GPIO_PIN_12);
|
|
GPIO_EXTI_Callback(GPIO_PIN_13);
|
|
GPIO_EXTI_Callback(GPIO_PIN_14);
|
|
GPIO_EXTI_Callback(GPIO_PIN_15);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
int rt_hw_pin_init(void)
|
|
{
|
|
int result;
|
|
|
|
|
|
#ifdef ES_INIT_GPIOS
|
|
|
|
rt_size_t i,gpio_conf_num = sizeof(gpio_conf_all) / sizeof(gpio_conf_t);
|
|
|
|
#endif
|
|
|
|
ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE);
|
|
|
|
result = rt_device_pin_register(ES_DEVICE_NAME_PIN, &_es32f0_pin_ops, RT_NULL);
|
|
|
|
if(result != RT_EOK)return result;
|
|
|
|
#ifdef ES_INIT_GPIOS
|
|
|
|
for(i = 0;i < gpio_conf_num;i++)
|
|
{
|
|
rt_pin_mode( gpio_conf_all[i].pin,gpio_conf_all[i].pin_mode);
|
|
|
|
if((gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT)||(gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT_OD))
|
|
rt_pin_write(gpio_conf_all[i].pin,gpio_conf_all[i].pin_level);
|
|
|
|
if(!gpio_conf_all[i].irq_en)continue;
|
|
|
|
rt_pin_attach_irq(gpio_conf_all[i].pin, gpio_conf_all[i].irq_mode, gpio_conf_all[i].callback, RT_NULL);
|
|
rt_pin_irq_enable(gpio_conf_all[i].pin, gpio_conf_all[i].irq_en);
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return result;
|
|
}
|
|
INIT_BOARD_EXPORT(rt_hw_pin_init);
|
|
|
|
#endif
|