645 lines
24 KiB
ArmAsm
645 lines
24 KiB
ArmAsm
/* ---------------------------------------------------------------------------------------*/
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/* @file: startup_LPC54114_cm0plus.S */
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/* @purpose: CMSIS Cortex-M0 Core Device Startup File */
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/* LPC54114_cm0plus */
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/* @version: 1.0 */
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/* @date: 2016-11-2 */
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/* @build: b161214 */
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/* ---------------------------------------------------------------------------------------*/
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/* */
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/* The Clear BSD License */
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/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
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/* Copyright 2016-2017 NXP */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without modification, */
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/* are permitted (subject to the limitations in the disclaimer below) provided */
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/* that the following conditions are met: */
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/* */
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/* 1. Redistributions of source code must retain the above copyright notice, this list */
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/* of conditions and the following disclaimer. */
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/* */
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/* 2. Redistributions in binary form must reproduce the above copyright notice, this */
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/* list of conditions and the following disclaimer in the documentation and/or */
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/* other materials provided with the distribution. */
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/* */
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/* 3. Neither the name of the copyright holder nor the names of its */
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/* contributors may be used to endorse or promote products derived from this */
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/* software without specific prior written permission. */
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/* */
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/* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S' PATENT RIGHTS ARE GRANTED BY THIS LICENSE.*/
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/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
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/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
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/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
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/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
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/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
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/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
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/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
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/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
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/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
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/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/*****************************************************************************/
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/* Version: GCC for ARM Embedded Processors */
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/*****************************************************************************/
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.syntax unified
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.arch armv7-m
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.section .isr_vector, "a"
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.align 2
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.globl __Vectors
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__Vectors:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler*/
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.long HardFault_Handler /* Hard Fault Handler*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long SVC_Handler /* SVCall Handler*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long PendSV_Handler /* PendSV Handler*/
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.long SysTick_Handler /* SysTick Handler*/
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/* External Interrupts*/
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.long WDT_BOD_IRQHandler /* Watchdog Timer, Brownout detect */
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.long DMA0_IRQHandler /* DMA controller interrupt */
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.long GINT0_IRQHandler /* GPIO group 0 */
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.long GINT1_IRQHandler /* GPIO group 1 */
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.long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */
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.long PIN_INT1_IRQHandler /* Pin interrupt 1 or pattern match engine slice 1 */
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.long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */
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.long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */
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.long UTICK0_IRQHandler /* Micro-tick Timer */
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.long MRT0_IRQHandler /* Multi-rate timer */
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.long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */
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.long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */
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.long SCT0_IRQHandler /* SCTimer/PWM */
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.long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */
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.long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
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.long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
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.long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
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.long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
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.long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
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.long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, FLEXCOMM) */
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.long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, FLEXCOMM) */
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.long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, FLEXCOMM) */
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.long ADC0_SEQA_IRQHandler /* ADC0 sequence A completion */
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.long ADC0_SEQB_IRQHandler /* ADC0 sequence B completion */
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.long ADC0_THCMP_IRQHandler /* ADC0 threshold compare and error. */
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.long DMIC0_IRQHandler /* RTC alarm and wake-up interrupts */
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.long HWVAD0_IRQHandler /* Hardware Voice Activity Detector */
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.long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */
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.long USB0_IRQHandler /* USB device */
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.long RTC_IRQHandler /* RTC alarm and wake-up interrupts */
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.long IOH_IRQHandler /* IOH interrupt */
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.long MAILBOX_IRQHandler /* Mailbox interrupt */
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.size __Vectors, . - __Vectors
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.text
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.thumb
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#ifndef SLAVEBOOT
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rel_vals:
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.long 0xE000ED00 /* cpu_id */
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.long 0x40000800 /* cpu_ctrl */
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.long 0x40000804 /* coproc_boot */
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.long 0x40000808 /* coproc_stack */
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.short 0x0FFF
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.short 0x0C24
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#endif
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/* Reset Handler */
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.thumb_func
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.align 2
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.globl Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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#ifndef SLAVEBOOT
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/* Both the M0+ and M4 core come via this shared startup code,
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* but the M0+ and M4 core have different vector tables.
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* Determine if the core executing this code is the master or
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* the slave and handle each core state individually. */
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shared_boot_entry:
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ldr r6, =rel_vals
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/* Flag for slave core (0) */
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movs r4, 0
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movs r5, 1
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/* Determine which core (M0+ or M4) this code is running on */
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/* r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) */
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get_current_core_id:
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ldr r0, [r6, #0]
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ldr r1, [r0] /* r1 = CPU ID status */
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lsrs r1, r1, #4 /* Right justify 12 CPU ID bits */
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ldrh r2, [r6, #16] /* Mask for CPU ID bits */
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ands r2, r1, r2 /* r2 = ARM COrtex CPU ID */
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ldrh r3, [r6, #18] /* Mask for CPU ID bits */
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cmp r3, r2 /* Core ID matches M4 identifier */
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bne get_master_status
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mov r4, r5 /* Set flag for master core (1) */
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/* Determine if M4 core is the master or slave */
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/* r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) */
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get_master_status:
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ldr r0, [r6, #4]
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ldr r3, [r0] /* r3 = SYSCON co-processor CPU control status */
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ands r3, r3, r5 /* r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) */
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/* Select boot based on selected master core and core ID */
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select_boot:
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eors r3, r3, r4 /* r4 = (Bit 0: 0 = master, 1 = slave) */
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bne slave_boot
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b normal_boot
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/* Slave boot */
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slave_boot:
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ldr r0, [r6, #8]
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ldr r2, [r0] /* r1 = SYSCON co-processor boot address */
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cmp r2, #0 /* Slave boot address = 0 (not set up)? */
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beq cpu_sleep
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ldr r0, [r6, #12]
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ldr r1, [r0] /* r5 = SYSCON co-processor stack address */
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mov sp, r1 /* Update slave CPU stack pointer */
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/* Be sure to update VTOR for the slave MCU to point to the */
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/* slave vector table in boot memory */
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bx r2 /* Jump to slave boot address */
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/* Slave isn't yet setup for system boot from the master */
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/* so sleep until the master sets it up and then reboots it */
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cpu_sleep:
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mov sp, r5 /* Will force exception if something happens */
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cpu_sleep_wfi:
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wfi /* Sleep forever until master reboots */
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b cpu_sleep_wfi
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#endif /* defined(SLAVEBOOT) */
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#ifndef __START
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#define __START _start
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#endif
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#ifndef __ATOLLIC__
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normal_boot:
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#ifndef __NO_SYSTEM_INIT
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ldr r0,=SystemInit
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blx r0
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#endif
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/* Loop to copy data from read only memory to RAM. The ranges
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* of copy from/to are specified by following symbols evaluated in
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* linker script.
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* __etext: End of code section, i.e., begin of data sections to copy from.
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* __data_start__/__data_end__: RAM address range that data should be
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* copied to. Both must be aligned to 4 bytes boundary. */
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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subs r3, r2
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ble .LC0
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.LC1:
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subs r3, 4
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ldr r0, [r1,r3]
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str r0, [r2,r3]
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bgt .LC1
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.LC0:
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#ifdef __STARTUP_CLEAR_BSS
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/* This part of work usually is done in C library startup code. Otherwise,
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* define this macro to enable it in this startup.
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*
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* Loop to zero out BSS section, which uses following symbols
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* in linker script:
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* __bss_start__: start of BSS section. Must align to 4
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* __bss_end__: end of BSS section. Must align to 4
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*/
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ldr r1, =__bss_start__
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ldr r2, =__bss_end__
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subs r2, r1
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ble .LC3
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movs r0, 0
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.LC2:
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str r0, [r1, r2]
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subs r2, 4
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bge .LC2
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.LC3:
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#endif /* __STARTUP_CLEAR_BSS */
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ldr r0,=__START
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blx r0
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#else
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ldr r0,=__libc_init_array
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blx r0
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ldr r0,=main
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bx r0
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#endif
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.pool
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.size Reset_Handler, . - Reset_Handler
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.align 1
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.thumb_func
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.weak DefaultISR
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.type DefaultISR, %function
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DefaultISR:
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b DefaultISR
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.size DefaultISR, . - DefaultISR
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.align 1
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.thumb_func
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.weak NMI_Handler
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.type NMI_Handler, %function
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NMI_Handler:
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ldr r0,=NMI_Handler
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bx r0
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.size NMI_Handler, . - NMI_Handler
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.align 1
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.thumb_func
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.weak HardFault_Handler
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.type HardFault_Handler, %function
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HardFault_Handler:
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ldr r0,=HardFault_Handler
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bx r0
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.size HardFault_Handler, . - HardFault_Handler
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.align 1
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.thumb_func
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.weak SVC_Handler
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.type SVC_Handler, %function
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SVC_Handler:
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ldr r0,=SVC_Handler
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bx r0
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.size SVC_Handler, . - SVC_Handler
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.align 1
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.thumb_func
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.weak PendSV_Handler
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.type PendSV_Handler, %function
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PendSV_Handler:
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ldr r0,=PendSV_Handler
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bx r0
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.size PendSV_Handler, . - PendSV_Handler
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.align 1
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.thumb_func
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.weak SysTick_Handler
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.type SysTick_Handler, %function
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SysTick_Handler:
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ldr r0,=SysTick_Handler
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bx r0
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.size SysTick_Handler, . - SysTick_Handler
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.align 1
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.thumb_func
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.weak WDT_BOD_IRQHandler
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.type WDT_BOD_IRQHandler, %function
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WDT_BOD_IRQHandler:
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ldr r0,=WDT_BOD_DriverIRQHandler
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bx r0
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.size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler
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.align 1
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.thumb_func
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.weak DMA0_IRQHandler
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.type DMA0_IRQHandler, %function
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DMA0_IRQHandler:
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ldr r0,=DMA0_DriverIRQHandler
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bx r0
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.size DMA0_IRQHandler, . - DMA0_IRQHandler
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.align 1
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.thumb_func
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.weak GINT0_IRQHandler
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.type GINT0_IRQHandler, %function
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GINT0_IRQHandler:
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ldr r0,=GINT0_DriverIRQHandler
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bx r0
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.size GINT0_IRQHandler, . - GINT0_IRQHandler
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.align 1
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.thumb_func
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.weak GINT1_IRQHandler
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.type GINT1_IRQHandler, %function
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GINT1_IRQHandler:
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ldr r0,=GINT1_DriverIRQHandler
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bx r0
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.size GINT1_IRQHandler, . - GINT1_IRQHandler
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.align 1
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.thumb_func
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.weak PIN_INT0_IRQHandler
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.type PIN_INT0_IRQHandler, %function
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PIN_INT0_IRQHandler:
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ldr r0,=PIN_INT0_DriverIRQHandler
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bx r0
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.size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler
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.align 1
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.thumb_func
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.weak PIN_INT1_IRQHandler
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.type PIN_INT1_IRQHandler, %function
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PIN_INT1_IRQHandler:
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ldr r0,=PIN_INT1_DriverIRQHandler
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bx r0
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.size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler
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.align 1
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.thumb_func
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.weak PIN_INT2_IRQHandler
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.type PIN_INT2_IRQHandler, %function
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PIN_INT2_IRQHandler:
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ldr r0,=PIN_INT2_DriverIRQHandler
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bx r0
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.size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler
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.align 1
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.thumb_func
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.weak PIN_INT3_IRQHandler
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.type PIN_INT3_IRQHandler, %function
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PIN_INT3_IRQHandler:
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ldr r0,=PIN_INT3_DriverIRQHandler
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bx r0
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.size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler
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.align 1
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.thumb_func
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.weak UTICK0_IRQHandler
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.type UTICK0_IRQHandler, %function
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UTICK0_IRQHandler:
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ldr r0,=UTICK0_DriverIRQHandler
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bx r0
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.size UTICK0_IRQHandler, . - UTICK0_IRQHandler
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.align 1
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.thumb_func
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.weak MRT0_IRQHandler
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.type MRT0_IRQHandler, %function
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MRT0_IRQHandler:
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ldr r0,=MRT0_DriverIRQHandler
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bx r0
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.size MRT0_IRQHandler, . - MRT0_IRQHandler
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.align 1
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.thumb_func
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.weak CTIMER0_IRQHandler
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.type CTIMER0_IRQHandler, %function
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CTIMER0_IRQHandler:
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ldr r0,=CTIMER0_DriverIRQHandler
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bx r0
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.size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler
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.align 1
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.thumb_func
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.weak CTIMER1_IRQHandler
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.type CTIMER1_IRQHandler, %function
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CTIMER1_IRQHandler:
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ldr r0,=CTIMER1_DriverIRQHandler
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bx r0
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.size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler
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.align 1
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.thumb_func
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.weak SCT0_IRQHandler
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.type SCT0_IRQHandler, %function
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SCT0_IRQHandler:
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ldr r0,=SCT0_DriverIRQHandler
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bx r0
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.size SCT0_IRQHandler, . - SCT0_IRQHandler
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.align 1
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.thumb_func
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.weak CTIMER3_IRQHandler
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.type CTIMER3_IRQHandler, %function
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CTIMER3_IRQHandler:
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ldr r0,=CTIMER3_DriverIRQHandler
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bx r0
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.size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler
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.align 1
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.thumb_func
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.weak FLEXCOMM0_IRQHandler
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.type FLEXCOMM0_IRQHandler, %function
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FLEXCOMM0_IRQHandler:
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ldr r0,=FLEXCOMM0_DriverIRQHandler
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bx r0
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.size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler
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.align 1
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.thumb_func
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.weak FLEXCOMM1_IRQHandler
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.type FLEXCOMM1_IRQHandler, %function
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FLEXCOMM1_IRQHandler:
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ldr r0,=FLEXCOMM1_DriverIRQHandler
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bx r0
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.size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler
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.align 1
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.thumb_func
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.weak FLEXCOMM2_IRQHandler
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.type FLEXCOMM2_IRQHandler, %function
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FLEXCOMM2_IRQHandler:
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ldr r0,=FLEXCOMM2_DriverIRQHandler
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bx r0
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.size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler
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.align 1
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.thumb_func
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.weak FLEXCOMM3_IRQHandler
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.type FLEXCOMM3_IRQHandler, %function
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FLEXCOMM3_IRQHandler:
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ldr r0,=FLEXCOMM3_DriverIRQHandler
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bx r0
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.size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler
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.align 1
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.thumb_func
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.weak FLEXCOMM4_IRQHandler
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.type FLEXCOMM4_IRQHandler, %function
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FLEXCOMM4_IRQHandler:
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ldr r0,=FLEXCOMM4_DriverIRQHandler
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bx r0
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.size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler
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.align 1
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.thumb_func
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.weak FLEXCOMM5_IRQHandler
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.type FLEXCOMM5_IRQHandler, %function
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FLEXCOMM5_IRQHandler:
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ldr r0,=FLEXCOMM5_DriverIRQHandler
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bx r0
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.size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler
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.align 1
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.thumb_func
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.weak FLEXCOMM6_IRQHandler
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.type FLEXCOMM6_IRQHandler, %function
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FLEXCOMM6_IRQHandler:
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ldr r0,=FLEXCOMM6_DriverIRQHandler
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bx r0
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.size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler
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.align 1
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.thumb_func
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.weak FLEXCOMM7_IRQHandler
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.type FLEXCOMM7_IRQHandler, %function
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FLEXCOMM7_IRQHandler:
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ldr r0,=FLEXCOMM7_DriverIRQHandler
|
|
bx r0
|
|
.size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler
|
|
|
|
|
|
.align 1
|
|
.thumb_func
|
|
.weak ADC0_SEQA_IRQHandler
|
|
.type ADC0_SEQA_IRQHandler, %function
|
|
ADC0_SEQA_IRQHandler:
|
|
ldr r0,=ADC0_SEQA_DriverIRQHandler
|
|
bx r0
|
|
.size ADC0_SEQA_IRQHandler, . - ADC0_SEQA_IRQHandler
|
|
|
|
.align 1
|
|
.thumb_func
|
|
.weak ADC0_SEQB_IRQHandler
|
|
.type ADC0_SEQB_IRQHandler, %function
|
|
ADC0_SEQB_IRQHandler:
|
|
ldr r0,=ADC0_SEQB_DriverIRQHandler
|
|
bx r0
|
|
.size ADC0_SEQB_IRQHandler, . - ADC0_SEQB_IRQHandler
|
|
|
|
.align 1
|
|
.thumb_func
|
|
.weak ADC0_THCMP_IRQHandler
|
|
.type ADC0_THCMP_IRQHandler, %function
|
|
ADC0_THCMP_IRQHandler:
|
|
ldr r0,=ADC0_THCMP_DriverIRQHandler
|
|
bx r0
|
|
.size ADC0_THCMP_IRQHandler, . - ADC0_THCMP_IRQHandler
|
|
|
|
.align 1
|
|
.thumb_func
|
|
.weak DMIC0_IRQHandler
|
|
.type DMIC0_IRQHandler, %function
|
|
DMIC0_IRQHandler:
|
|
ldr r0,=DMIC0_DriverIRQHandler
|
|
bx r0
|
|
.size DMIC0_IRQHandler, . - DMIC0_IRQHandler
|
|
|
|
.align 1
|
|
.thumb_func
|
|
.weak HWVAD0_IRQHandler
|
|
.type HWVAD0_IRQHandler, %function
|
|
HWVAD0_IRQHandler:
|
|
ldr r0,=HWVAD0_DriverIRQHandler
|
|
bx r0
|
|
.size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler
|
|
|
|
.align 1
|
|
.thumb_func
|
|
.weak USB0_NEEDCLK_IRQHandler
|
|
.type USB0_NEEDCLK_IRQHandler, %function
|
|
USB0_NEEDCLK_IRQHandler:
|
|
ldr r0,=USB0_NEEDCLK_DriverIRQHandler
|
|
bx r0
|
|
.size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler
|
|
|
|
.align 1
|
|
.thumb_func
|
|
.weak USB0_IRQHandler
|
|
.type USB0_IRQHandler, %function
|
|
USB0_IRQHandler:
|
|
ldr r0,=USB0_DriverIRQHandler
|
|
bx r0
|
|
.size USB0_IRQHandler, . - USB0_IRQHandler
|
|
|
|
.align 1
|
|
.thumb_func
|
|
.weak RTC_IRQHandler
|
|
.type RTC_IRQHandler, %function
|
|
RTC_IRQHandler:
|
|
ldr r0,=RTC_DriverIRQHandler
|
|
bx r0
|
|
.size RTC_IRQHandler, . - RTC_IRQHandler
|
|
|
|
.align 1
|
|
.thumb_func
|
|
.weak IOH_IRQHandler
|
|
.type IOH_IRQHandler, %function
|
|
IOH_IRQHandler:
|
|
ldr r0,=IOH_DriverIRQHandler
|
|
bx r0
|
|
.size IOH_IRQHandler, . - IOH_IRQHandler
|
|
|
|
.align 1
|
|
.thumb_func
|
|
.weak MAILBOX_IRQHandler
|
|
.type MAILBOX_IRQHandler, %function
|
|
MAILBOX_IRQHandler:
|
|
ldr r0,=MAILBOX_DriverIRQHandler
|
|
bx r0
|
|
.size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler
|
|
|
|
|
|
/* Macro to define default handlers. Default handler
|
|
* will be weak symbol and just dead loops. They can be
|
|
* overwritten by other handlers */
|
|
.macro def_irq_handler handler_name
|
|
.weak \handler_name
|
|
.set \handler_name, DefaultISR
|
|
.endm
|
|
|
|
/* Exception Handlers */
|
|
def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect */
|
|
def_irq_handler DMA0_DriverIRQHandler /* DMA controller */
|
|
def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */
|
|
def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */
|
|
def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */
|
|
def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */
|
|
def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */
|
|
def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */
|
|
def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */
|
|
def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */
|
|
def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */
|
|
def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */
|
|
def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */
|
|
def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */
|
|
def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C) */
|
|
def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C) */
|
|
def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C) */
|
|
def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C) */
|
|
def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C) */
|
|
def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C) */
|
|
def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S) */
|
|
def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S) */
|
|
def_irq_handler ADC0_SEQA_DriverIRQHandler /* ADC0 sequence A completion. */
|
|
def_irq_handler ADC0_SEQB_DriverIRQHandler /* ADC0 sequence B completion. */
|
|
def_irq_handler ADC0_THCMP_DriverIRQHandler /* ADC0 threshold compare and error. */
|
|
def_irq_handler DMIC0_DriverIRQHandler /* Digital microphone and DMIC subsystem */
|
|
def_irq_handler HWVAD0_DriverIRQHandler /* Hardware Voice sActivity Detector */
|
|
def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */
|
|
def_irq_handler USB0_DriverIRQHandler /* USB device */
|
|
def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */
|
|
def_irq_handler IOH_DriverIRQHandler /* IOH */
|
|
def_irq_handler MAILBOX_DriverIRQHandler /* Mailbox interrupt (present on selected devices) */
|
|
|
|
.end
|