537 lines
20 KiB
C
537 lines
20 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_ACMP_H_
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#define _FSL_ACMP_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup acmp
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief ACMP driver version 2.0.6. */
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#define FSL_ACMP_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 6U))
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/*@}*/
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/*! @brief The mask of status flags cleared by writing 1. */
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#define CMP_C0_CFx_MASK (CMP_C0_CFR_MASK | CMP_C0_CFF_MASK)
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#define CMP_C1_CHNn_MASK 0xFF0000U /* C1_CHN0 - C1_CHN7. */
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#define CMP_C2_CHnF_MASK 0xFF0000U /* C2_CH0F - C2_CH7F. */
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/*! @brief Interrupt enable/disable mask. */
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enum _acmp_interrupt_enable
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{
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kACMP_OutputRisingInterruptEnable = (1U << 0U), /*!< Enable the interrupt when comparator outputs rising. */
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kACMP_OutputFallingInterruptEnable = (1U << 1U), /*!< Enable the interrupt when comparator outputs falling. */
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kACMP_RoundRobinInterruptEnable = (1U << 2U), /*!< Enable the Round-Robin interrupt. */
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};
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/*! @brief Status flag mask. */
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enum _acmp_status_flags
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{
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kACMP_OutputRisingEventFlag = CMP_C0_CFR_MASK, /*!< Rising-edge on compare output has occurred. */
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kACMP_OutputFallingEventFlag = CMP_C0_CFF_MASK, /*!< Falling-edge on compare output has occurred. */
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kACMP_OutputAssertEventFlag = CMP_C0_COUT_MASK, /*!< Return the current value of the analog comparator output. */
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};
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#if defined(FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT) && (FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT == 1U)
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/*!
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* @brief Comparator hard block offset control.
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*
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* If OFFSET level is 1, then there is no hysteresis in the case of positive port input crossing negative port
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* input in the positive direction (or negative port input crossing positive port input in the negative direction).
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* Hysteresis still exists for positive port input crossing negative port input in the falling direction.
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* If OFFSET level is 0, then the hysteresis selected by acmp_hysteresis_mode_t is valid for both directions.
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*/
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typedef enum _acmp_offset_mode
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{
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kACMP_OffsetLevel0 = 0U, /*!< The comparator hard block output has level 0 offset internally. */
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kACMP_OffsetLevel1 = 1U, /*!< The comparator hard block output has level 1 offset internally. */
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} acmp_offset_mode_t;
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#endif /* FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT */
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/*!
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* @brief Comparator hard block hysteresis control.
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*
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* See chip data sheet to get the actual hysteresis value with each level.
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*/
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typedef enum _acmp_hysteresis_mode
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{
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kACMP_HysteresisLevel0 = 0U, /*!< Offset is level 0 and Hysteresis is level 0. */
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kACMP_HysteresisLevel1 = 1U, /*!< Offset is level 0 and Hysteresis is level 1. */
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kACMP_HysteresisLevel2 = 2U, /*!< Offset is level 0 and Hysteresis is level 2. */
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kACMP_HysteresisLevel3 = 3U, /*!< Offset is level 0 and Hysteresis is level 3. */
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} acmp_hysteresis_mode_t;
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/*! @brief CMP Voltage Reference source. */
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typedef enum _acmp_reference_voltage_source
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{
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kACMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as resistor ladder network supply reference Vin. */
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kACMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as resistor ladder network supply reference Vin. */
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} acmp_reference_voltage_source_t;
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#if defined(FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT) && (FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT == 1U)
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/*! @brief Port input source. */
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typedef enum _acmp_port_input
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{
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kACMP_PortInputFromDAC = 0U, /*!< Port input from the 8-bit DAC output. */
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kACMP_PortInputFromMux = 1U, /*!< Port input from the analog 8-1 mux. */
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} acmp_port_input_t;
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#endif /* FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT */
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/*! @brief Fixed mux port. */
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typedef enum _acmp_fixed_port
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{
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kACMP_FixedPlusPort = 0U, /*!< Only the inputs to the Minus port are swept in each round. */
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kACMP_FixedMinusPort = 1U, /*!< Only the inputs to the Plus port are swept in each round. */
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} acmp_fixed_port_t;
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#if defined(FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT) && (FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT == 1U)
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/*! @brief Internal DAC's work mode. */
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typedef enum _acmp_dac_work_mode
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{
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kACMP_DACWorkLowSpeedMode = 0U, /*!< DAC is selected to work in low speed and low power mode. */
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kACMP_DACWorkHighSpeedMode = 1U, /*!< DAC is selected to work in high speed high power mode. */
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} acmp_dac_work_mode_t;
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#endif /* FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT */
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/*! @brief Configuration for ACMP. */
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typedef struct _acmp_config
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{
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#if defined(FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT) && (FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT == 1U)
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acmp_offset_mode_t offsetMode; /*!< Offset mode. */
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#endif /* FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT */
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acmp_hysteresis_mode_t hysteresisMode; /*!< Hysteresis mode. */
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bool enableHighSpeed; /*!< Enable High Speed (HS) comparison mode. */
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bool enableInvertOutput; /*!< Enable inverted comparator output. */
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bool useUnfilteredOutput; /*!< Set compare output(COUT) to equal COUTA(true) or COUT(false). */
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bool enablePinOut; /*!< The comparator output is available on the associated pin. */
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} acmp_config_t;
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/*!
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* @brief Configuration for channel.
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*
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* The comparator's port can be input from channel mux or DAC. If port input is from channel mux, detailed channel
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* number for the mux should be configured.
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*/
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typedef struct _acmp_channel_config
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{
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#if defined(FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT) && (FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT == 1U)
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acmp_port_input_t positivePortInput; /*!< Input source of the comparator's positive port. */
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#endif /* FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT */
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uint32_t plusMuxInput; /*!< Plus mux input channel(0~7). */
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#if defined(FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT) && (FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT == 1U)
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acmp_port_input_t negativePortInput; /*!< Input source of the comparator's negative port. */
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#endif /* FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT */
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uint32_t minusMuxInput; /*!< Minus mux input channel(0~7). */
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} acmp_channel_config_t;
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/*! @brief Configuration for filter. */
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typedef struct _acmp_filter_config
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{
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bool enableSample; /*!< Using external SAMPLE as sampling clock input, or using divided bus clock. */
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uint32_t filterCount; /*!< Filter Sample Count. Available range is 1-7, 0 would cause the filter disabled. */
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uint32_t filterPeriod; /*!< Filter Sample Period. The divider to bus clock. Available range is 0-255. */
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} acmp_filter_config_t;
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/*! @brief Configuration for DAC. */
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typedef struct _acmp_dac_config
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{
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acmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */
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uint32_t DACValue; /*!< Value for DAC Output Voltage. Available range is 0-255. */
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#if defined(FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT) && (FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT == 1U)
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bool enableOutput; /*!< Enable the DAC output. */
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#endif /* FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT */
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#if defined(FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT) && (FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT == 1U)
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acmp_dac_work_mode_t workMode;
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#endif /* FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT */
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} acmp_dac_config_t;
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/*! @brief Configuration for round robin mode. */
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typedef struct _acmp_round_robin_config
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{
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acmp_fixed_port_t fixedPort; /*!< Fixed mux port. */
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uint32_t fixedChannelNumber; /*!< Indicates which channel is fixed in the fixed mux port. */
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uint32_t checkerChannelMask; /*!< Mask of checker channel index. Available range is channel0:0x01 to channel7:0x80
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for round-robin checker. */
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uint32_t sampleClockCount; /*!< Specifies how many round-robin clock cycles(0~3) later the sample takes place. */
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uint32_t delayModulus; /*!< Comparator and DAC initialization delay modulus. */
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} acmp_round_robin_config_t;
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#if defined(FSL_FEATURE_ACMP_HAS_C3_REG) && (FSL_FEATURE_ACMP_HAS_C3_REG == 1U)
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/*! @brief Discrete mode clock selection. */
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typedef enum _acmp_discrete_clock_source
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{
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kACMP_DiscreteClockSlow = 0U, /*!< Slow clock (32kHz) is used as the discrete mode clock. */
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kACMP_DiscreteClockFast = 1U, /*!< Fast clock (16-20MHz) is used as the discrete mode clock. */
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} acmp_discrete_clock_source_t;
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/*!
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* @brief ACMP discrete sample selection.
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* These values configures the analog comparator sampling timing (speicified by the discrete mode clock period T which
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* is selected by #acmp_discrete_clock_source_t) in discrete mode.
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*/
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typedef enum _acmp_discrete_sample_time
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{
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kACMP_DiscreteSampleTimeAs1T = 0U, /*!< The sampling time equals to 1xT. */
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kACMP_DiscreteSampleTimeAs2T = 1U, /*!< The sampling time equals to 2xT. */
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kACMP_DiscreteSampleTimeAs4T = 2U, /*!< The sampling time equals to 4xT. */
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kACMP_DiscreteSampleTimeAs8T = 3U, /*!< The sampling time equals to 8xT. */
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kACMP_DiscreteSampleTimeAs16T = 4U, /*!< The sampling time equals to 16xT. */
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kACMP_DiscreteSampleTimeAs32T = 5U, /*!< The sampling time equals to 32xT. */
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kACMP_DiscreteSampleTimeAs64T = 6U, /*!< The sampling time equals to 64xT. */
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kACMP_DiscreteSampleTimeAs256T = 7U, /*!< The sampling time equals to 256xT. */
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} acmp_discrete_sample_time_t;
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/*!
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* @brief ACMP discrete phase time selection.
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* There are two phases for sampling input signals, phase 1 and phase 2.
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*/
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typedef enum _acmp_discrete_phase_time
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{
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kACMP_DiscretePhaseTimeAlt0 = 0U, /*!< The phase x active in one sampling selection 0. */
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kACMP_DiscretePhaseTimeAlt1 = 1U, /*!< The phase x active in one sampling selection 1. */
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kACMP_DiscretePhaseTimeAlt2 = 2U, /*!< The phase x active in one sampling selection 2. */
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kACMP_DiscretePhaseTimeAlt3 = 3U, /*!< The phase x active in one sampling selection 3. */
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kACMP_DiscretePhaseTimeAlt4 = 4U, /*!< The phase x active in one sampling selection 4. */
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kACMP_DiscretePhaseTimeAlt5 = 5U, /*!< The phase x active in one sampling selection 5. */
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kACMP_DiscretePhaseTimeAlt6 = 6U, /*!< The phase x active in one sampling selection 6. */
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kACMP_DiscretePhaseTimeAlt7 = 7U, /*!< The phase x active in one sampling selection 7. */
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} acmp_discrete_phase_time_t;
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/*! @brief Configuration for discrete mode. */
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typedef struct _acmp_discrete_mode_config
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{
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bool enablePositiveChannelDiscreteMode; /*!< Positive Channel Continuous Mode Enable. By default, the continuous
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mode is used. */
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bool enableNegativeChannelDiscreteMode; /*!< Negative Channel Continuous Mode Enable. By default, the continuous
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mode is used. */
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bool enableResistorDivider; /*!< Resistor Divider Enable is used to enable the resistor divider for the inputs when
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they come from 3v domain and their values are above 1.8v. */
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acmp_discrete_clock_source_t clockSource; /*!< Select the clock source in order to generate the requiried timing for
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comparator to work in discrete mode. */
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acmp_discrete_sample_time_t sampleTime; /*!< Select the ACMP total sampling time period. */
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acmp_discrete_phase_time_t phase1Time; /*!< Select the ACMP phase 1 sampling time. */
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acmp_discrete_phase_time_t phase2Time; /*!< Select the ACMP phase 2 sampling time. */
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} acmp_discrete_mode_config_t;
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#endif /* FSL_FEATURE_ACMP_HAS_C3_REG */
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*******************************************************************************
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* API
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******************************************************************************/
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/*!
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* @name Initialization and deinitialization
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* @{
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*/
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/*!
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* @brief Initializes the ACMP.
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*
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* The default configuration can be got by calling ACMP_GetDefaultConfig().
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*
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* @param base ACMP peripheral base address.
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* @param config Pointer to ACMP configuration structure.
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*/
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void ACMP_Init(CMP_Type *base, const acmp_config_t *config);
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/*!
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* @brief Deinitializes the ACMP.
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*
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* @param base ACMP peripheral base address.
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*/
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void ACMP_Deinit(CMP_Type *base);
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/*!
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* @brief Gets the default configuration for ACMP.
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*
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* This function initializes the user configuration structure to default value. The default value are:
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*
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* Example:
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@code
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config->enableHighSpeed = false;
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config->enableInvertOutput = false;
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config->useUnfilteredOutput = false;
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config->enablePinOut = false;
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config->enableHysteresisBothDirections = false;
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config->hysteresisMode = kACMP_hysteresisMode0;
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@endcode
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*
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* @param config Pointer to ACMP configuration structure.
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*/
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void ACMP_GetDefaultConfig(acmp_config_t *config);
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/* @} */
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/*!
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* @name Basic Operations
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* @{
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*/
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/*!
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* @brief Enables or disables the ACMP.
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*
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* @param base ACMP peripheral base address.
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* @param enable True to enable the ACMP.
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*/
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void ACMP_Enable(CMP_Type *base, bool enable);
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#if defined(FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT) && (FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT == 1U)
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/*!
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* @brief Enables the link from CMP to DAC enable.
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*
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* When this bit is set, the DAC enable/disable is controlled by the bit CMP_C0[EN] instead of CMP_C1[DACEN].
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*
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* @param base ACMP peripheral base address.
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* @param enable Enable the feature or not.
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*/
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void ACMP_EnableLinkToDAC(CMP_Type *base, bool enable);
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#endif /* FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT */
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/*!
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* @brief Sets the channel configuration.
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*
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* Note that the plus/minus mux's setting is only valid when the positive/negative port's input isn't from DAC but
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* from channel mux.
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*
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* Example:
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@code
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acmp_channel_config_t configStruct = {0};
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configStruct.positivePortInput = kACMP_PortInputFromDAC;
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configStruct.negativePortInput = kACMP_PortInputFromMux;
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configStruct.minusMuxInput = 1U;
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ACMP_SetChannelConfig(CMP0, &configStruct);
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@endcode
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*
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* @param base ACMP peripheral base address.
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* @param config Pointer to channel configuration structure.
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*/
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void ACMP_SetChannelConfig(CMP_Type *base, const acmp_channel_config_t *config);
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/* @} */
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/*!
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* @name Advanced Operations
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* @{
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*/
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/*!
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* @brief Enables or disables DMA.
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*
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* @param base ACMP peripheral base address.
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* @param enable True to enable DMA.
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*/
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void ACMP_EnableDMA(CMP_Type *base, bool enable);
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/*!
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* @brief Enables or disables window mode.
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*
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* @param base ACMP peripheral base address.
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* @param enable True to enable window mode.
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*/
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void ACMP_EnableWindowMode(CMP_Type *base, bool enable);
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/*!
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* @brief Configures the filter.
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*
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* The filter can be enabled when the filter count is bigger than 1, the filter period is greater than 0 and the sample
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* clock is from divided bus clock or the filter is bigger than 1 and the sample clock is from external clock. Detailed
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* usage can be got from the reference manual.
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*
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* Example:
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@code
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acmp_filter_config_t configStruct = {0};
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configStruct.filterCount = 5U;
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configStruct.filterPeriod = 200U;
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configStruct.enableSample = false;
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ACMP_SetFilterConfig(CMP0, &configStruct);
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@endcode
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*
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* @param base ACMP peripheral base address.
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* @param config Pointer to filter configuration structure.
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*/
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void ACMP_SetFilterConfig(CMP_Type *base, const acmp_filter_config_t *config);
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/*!
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* @brief Configures the internal DAC.
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*
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* Example:
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@code
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acmp_dac_config_t configStruct = {0};
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configStruct.referenceVoltageSource = kACMP_VrefSourceVin1;
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configStruct.DACValue = 20U;
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configStruct.enableOutput = false;
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configStruct.workMode = kACMP_DACWorkLowSpeedMode;
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ACMP_SetDACConfig(CMP0, &configStruct);
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@endcode
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*
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* @param base ACMP peripheral base address.
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* @param config Pointer to DAC configuration structure. "NULL" is for disabling the feature.
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*/
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void ACMP_SetDACConfig(CMP_Type *base, const acmp_dac_config_t *config);
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/*!
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* @brief Configures the round robin mode.
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*
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* Example:
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@code
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acmp_round_robin_config_t configStruct = {0};
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configStruct.fixedPort = kACMP_FixedPlusPort;
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configStruct.fixedChannelNumber = 3U;
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configStruct.checkerChannelMask = 0xF7U;
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configStruct.sampleClockCount = 0U;
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configStruct.delayModulus = 0U;
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ACMP_SetRoundRobinConfig(CMP0, &configStruct);
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@endcode
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* @param base ACMP peripheral base address.
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* @param config Pointer to round robin mode configuration structure. "NULL" is for disabling the feature.
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*/
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void ACMP_SetRoundRobinConfig(CMP_Type *base, const acmp_round_robin_config_t *config);
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/*!
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* @brief Defines the pre-set state of channels in round robin mode.
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*
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* Note: The pre-state has different circuit with get-round-robin-result in the SOC even though they are same bits.
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* So get-round-robin-result can't return the same value as the value are set by pre-state.
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*
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* @param base ACMP peripheral base address.
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* @param mask Mask of round robin channel index. Available range is channel0:0x01 to channel7:0x80.
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*/
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void ACMP_SetRoundRobinPreState(CMP_Type *base, uint32_t mask);
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/*!
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* @brief Gets the channel input changed flags in round robin mode.
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*
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* @param base ACMP peripheral base address.
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* @return Mask of channel input changed asserted flags. Available range is channel0:0x01 to channel7:0x80.
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*/
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static inline uint32_t ACMP_GetRoundRobinStatusFlags(CMP_Type *base)
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{
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return (((base->C2) & CMP_C2_CHnF_MASK) >> CMP_C2_CH0F_SHIFT);
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}
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/*!
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* @brief Clears the channel input changed flags in round robin mode.
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*
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* @param base ACMP peripheral base address.
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* @param mask Mask of channel index. Available range is channel0:0x01 to channel7:0x80.
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*/
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void ACMP_ClearRoundRobinStatusFlags(CMP_Type *base, uint32_t mask);
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/*!
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* @brief Gets the round robin result.
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*
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* Note that the set-pre-state has different circuit with get-round-robin-result in the SOC even though they are same
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* bits. So ACMP_GetRoundRobinResult() can't return the same value as the value are set by ACMP_SetRoundRobinPreState.
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|
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* @param base ACMP peripheral base address.
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* @return Mask of round robin channel result. Available range is channel0:0x01 to channel7:0x80.
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*/
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static inline uint32_t ACMP_GetRoundRobinResult(CMP_Type *base)
|
|
{
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return ((base->C2 & CMP_C2_ACOn_MASK) >> CMP_C2_ACOn_SHIFT);
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}
|
|
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/* @} */
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|
|
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/*!
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|
* @name Interrupts
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|
* @{
|
|
*/
|
|
|
|
/*!
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|
* @brief Enables interrupts.
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|
*
|
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* @param base ACMP peripheral base address.
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|
* @param mask Interrupts mask. See "_acmp_interrupt_enable".
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|
*/
|
|
void ACMP_EnableInterrupts(CMP_Type *base, uint32_t mask);
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|
|
|
/*!
|
|
* @brief Disables interrupts.
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|
*
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|
* @param base ACMP peripheral base address.
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|
* @param mask Interrupts mask. See "_acmp_interrupt_enable".
|
|
*/
|
|
void ACMP_DisableInterrupts(CMP_Type *base, uint32_t mask);
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|
|
|
/* @} */
|
|
|
|
/*!
|
|
* @name Status
|
|
* @{
|
|
*/
|
|
|
|
/*!
|
|
* @brief Gets status flags.
|
|
*
|
|
* @param base ACMP peripheral base address.
|
|
* @return Status flags asserted mask. See "_acmp_status_flags".
|
|
*/
|
|
uint32_t ACMP_GetStatusFlags(CMP_Type *base);
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|
|
|
/*!
|
|
* @brief Clears status flags.
|
|
*
|
|
* @param base ACMP peripheral base address.
|
|
* @param mask Status flags mask. See "_acmp_status_flags".
|
|
*/
|
|
void ACMP_ClearStatusFlags(CMP_Type *base, uint32_t mask);
|
|
|
|
/* @} */
|
|
|
|
#if defined(FSL_FEATURE_ACMP_HAS_C3_REG) && (FSL_FEATURE_ACMP_HAS_C3_REG == 1U)
|
|
/*!
|
|
* @name Discrete mode
|
|
* @{
|
|
*/
|
|
|
|
/*!
|
|
* @brief Configure the discrete mode.
|
|
*
|
|
* Configure the discrete mode when supporting 3V domain with 1.8V core.
|
|
*
|
|
* @param base ACMP peripheral base address.
|
|
* @param config Pointer to configuration structure. See "acmp_discrete_mode_config_t".
|
|
*/
|
|
void ACMP_SetDiscreteModeConfig(CMP_Type *base, const acmp_discrete_mode_config_t *config);
|
|
|
|
/*!
|
|
* @brief Get the default configuration for discrete mode setting.
|
|
*
|
|
* @param config Pointer to configuration structure to be restored with the setting values.
|
|
*/
|
|
void ACMP_GetDefaultDiscreteModeConfig(acmp_discrete_mode_config_t *config);
|
|
|
|
/* @} */
|
|
#endif /* FSL_FEATURE_ACMP_HAS_C3_REG */
|
|
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif
|
|
|
|
/*! @}*/
|
|
|
|
#endif /* _FSL_ACMP_H_ */
|