119 lines
3.2 KiB
C
119 lines
3.2 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-3-08 GuEe-GUI the first version
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*/
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#ifndef __RK3568_H__
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#define __RK3568_H__
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#include <rtthread.h>
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/* UART */
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#define UART_MMIO_BASE 0xfe650000
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#define UART0_MMIO_BASE 0xfdd50000
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#define UART1_MMIO_BASE (UART_MMIO_BASE + 0)
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#define UART2_MMIO_BASE (UART_MMIO_BASE + 0x10000)
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#define UART3_MMIO_BASE (UART_MMIO_BASE + 0x20000)
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#define UART4_MMIO_BASE (UART_MMIO_BASE + 0x30000)
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#define UART5_MMIO_BASE (UART_MMIO_BASE + 0x40000)
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#define UART6_MMIO_BASE (UART_MMIO_BASE + 0x50000)
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#define UART7_MMIO_BASE (UART_MMIO_BASE + 0x60000)
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#define UART8_MMIO_BASE (UART_MMIO_BASE + 0x70000)
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#define UART9_MMIO_BASE (UART_MMIO_BASE + 0x80000)
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#define UART_MMIO_SIZE 0x100
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#define UART_IRQ_BASE (32 + 116)
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#define UART0_IRQ (UART_IRQ_BASE + 0)
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#define UART1_IRQ (UART_IRQ_BASE + 1)
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#define UART2_IRQ (UART_IRQ_BASE + 2)
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#define UART3_IRQ (UART_IRQ_BASE + 3)
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#define UART4_IRQ (UART_IRQ_BASE + 4)
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#define UART5_IRQ (UART_IRQ_BASE + 5)
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#define UART6_IRQ (UART_IRQ_BASE + 6)
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#define UART7_IRQ (UART_IRQ_BASE + 7)
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#define UART8_IRQ (UART_IRQ_BASE + 8)
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#define UART9_IRQ (UART_IRQ_BASE + 9)
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/* GPIO */
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#define GPIO0_MMIO_BASE 0xfdd60000
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#define GPIO1_MMIO_BASE 0xfe740000
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#define GPIO2_MMIO_BASE 0xfe750000
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#define GPIO3_MMIO_BASE 0xfe760000
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#define GPIO4_MMIO_BASE 0xfe770000
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#define GPIO_MMIO_SIZE 0x100
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#define GPIO_IRQ_BASE (32 + 33)
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#define GPIO0_IRQ (GPIO_IRQ_BASE + 0)
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#define GPIO1_IRQ (GPIO_IRQ_BASE + 1)
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#define GPIO2_IRQ (GPIO_IRQ_BASE + 2)
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#define GPIO3_IRQ (GPIO_IRQ_BASE + 3)
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#define GPIO4_IRQ (GPIO_IRQ_BASE + 4)
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/* MMC */
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#define MMC0_MMIO_BASE 0xfe310000 /* sdhci */
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#define MMC1_MMIO_BASE 0xfe2b0000 /* sdmmc0 */
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#define MMC2_MMIO_BASE 0xfe2c0000 /* sdmmc1 */
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#define MMC3_MMIO_BASE 0xfe000000 /* sdmmc2 */
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#define MMC0_MMIO_SIZE 0x10000
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#define MMC_MMIO_SIZE 0x4000
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#define MMC0_IRQ (32 + 19)
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#define MMC1_IRQ (32 + 98)
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#define MMC2_IRQ (32 + 99)
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#define MMC3_IRQ (32 + 100)
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/* Ethernet */
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#define GMAC0_MMIO_BASE 0xfe2a0000
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#define GMAC1_MMIO_BASE 0xfe010000
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#define GMAC_MMIO_SIZE 0x10000
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#define GMAC0_MAC_IRQ (32 + 27)
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#define GMAC0_WAKE_IRQ (32 + 24)
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#define GMAC1_MAC_IRQ (32 + 32)
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#define GMAC1_WAKE_IRQ (32 + 29)
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/* GIC */
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#define MAX_HANDLERS 256
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#define GIC_IRQ_START 0
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#define ARM_GIC_NR_IRQS 256
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#define ARM_GIC_MAX_NR 1
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#define IRQ_ARM_IPI_KICK 0
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#define IRQ_ARM_IPI_CALL 1
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#define GIC_PL600_DISTRIBUTOR_PPTR 0xfd400000
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#define GIC_PL600_REDISTRIBUTOR_PPTR 0xfd460000
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#define GIC_PL600_CONTROLLER_PPTR RT_NULL
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#define GIC_PL600_ITS_PPTR 0xfd440000
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rt_inline rt_uint32_t platform_get_gic_dist_base(void)
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{
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return GIC_PL600_DISTRIBUTOR_PPTR;
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}
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rt_inline rt_uint32_t platform_get_gic_redist_base(void)
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{
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return GIC_PL600_REDISTRIBUTOR_PPTR;
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}
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rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
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{
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return GIC_PL600_CONTROLLER_PPTR;
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}
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rt_inline rt_uint32_t platform_get_gic_its_base(void)
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{
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return GIC_PL600_ITS_PPTR;
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}
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#endif /* __RK3568_H__ */
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