848 lines
26 KiB
C
848 lines
26 KiB
C
//*****************************************************************************
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//
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// am_hal_sysctrl.c
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//! @file
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//!
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//! @brief Functions for interfacing with the M4F system control registers
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//!
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//! @addtogroup sysctrl2 System Control (SYSCTRL)
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//! @ingroup apollo2hal
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#include <stdint.h>
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#include <stdbool.h>
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#include "am_mcu_apollo.h"
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//*****************************************************************************
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//
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// Local macro constants
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//
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//*****************************************************************************
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//
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// Define ZX workaround values.
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// These values are defined by the factory.
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//
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#define COREZXVALUE 0x07
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#define MEMZXVALUE 0x07
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//
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// Define values for g_ui32CoreBuck, which indicates which timer carries
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// the signal for the CORE Buck, and which also implies that the other timer
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// carries the signal for the MEM buck.
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//
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#define COREBUCK_TIMERA 1 // Core buck signal comes in on timer A
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#define COREBUCK_TIMERB 2 // Core buck signal comes in on timer B
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//
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// Define the bit values for static function g_buckZX_chk;
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//
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#define CHKBUCKZX_BUCKS 0x01 // The bucks are enabled
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#define CHKBUCKZX_REV 0x02 // This chip rev needs the workaround
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#define CHKBUCKZX_TIMER 0x04 // A valid timer has been allocated
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#define CHKBUCKZX_DEVEN 0x08 // Devices are powered up and enabled
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//*****************************************************************************
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//
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// Prototypes
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//
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//*****************************************************************************
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static void am_hal_sysctrl_buckA_ctimer_isr(void);
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static void am_hal_sysctrl_buckB_ctimer_isr(void);
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//*****************************************************************************
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//
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// Globals
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//
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//*****************************************************************************
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static volatile uint32_t g_ui32BuckTimer = 0;
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static volatile uint32_t g_ui32BuckInputs = 0;
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static volatile bool g_bBuckRestoreComplete = false;
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static volatile bool g_bBuckTimed = false;
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static uint32_t g_ui32SaveCoreBuckZX, g_ui32SaveMemBuckZX;
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static uint32_t g_buckZX_chk = 0;
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static volatile uint32_t g_ui32CoreBuck;
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//
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// Timer configuration for BUCK inputs.
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//
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static const am_hal_ctimer_config_t g_sBuckTimer =
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{
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// Don't link timers.
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0,
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// Set up Timer0A.
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(AM_HAL_CTIMER_FN_ONCE |
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AM_HAL_CTIMER_INT_ENABLE |
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AM_HAL_CTIMER_BUCK),
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// Set up Timer0B.
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(AM_HAL_CTIMER_FN_ONCE |
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AM_HAL_CTIMER_INT_ENABLE |
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AM_HAL_CTIMER_BUCK),
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};
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//*****************************************************************************
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//
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// Determine if we need to do the zero cross workaround on this device.
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// Three criteria are used. All three must be true.
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// 1. Are the bucks enabled?
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// 2. Is the chip rev appropriate for the workaround?
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// 3. Has a timer been allocated to do the workaround?
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// 4. Are certain peripherals powered up?
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//
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// Saves the bitmask to the global g_buckZX_chk.
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// Bitmask bits are defined as: CHKBUCKZX_BUCKS, CHKBUCKZX_REV, CHKBUCKZX_TIMER.
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//
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// Returns true if all criteria are met, false otherwise.
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// g_buckZX_chk can be probed to determine which criteria passed or failed.
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//
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//*****************************************************************************
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static bool
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buckZX_chk(void)
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{
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uint32_t ui32SupplySrc;
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//
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// Is this chip rev appropriate to do the workaround?
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//
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g_buckZX_chk = AM_BFM(MCUCTRL, CHIPREV, REVMAJ) == AM_REG_MCUCTRL_CHIPREV_REVMAJ_B ?
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CHKBUCKZX_REV : 0x0;
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//
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// Has a timer been configured to handle the workaround?
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//
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g_buckZX_chk |= ( g_ui32BuckTimer - 1 ) <= BUCK_TIMER_MAX ?
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CHKBUCKZX_TIMER : 0x0;
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//
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// Are either or both of the bucks actually enabled?
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//
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ui32SupplySrc = AM_REG(PWRCTRL, SUPPLYSRC);
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g_buckZX_chk |= (ui32SupplySrc &
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(AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN_M |
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AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_M) ) ?
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CHKBUCKZX_BUCKS : 0x0;
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//
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// Finally, if any peripheral is already powered up, we don't need to do the
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// ZX workaround because in this case the bucks remain in active mode.
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//
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ui32SupplySrc = AM_REG(PWRCTRL, DEVICEEN);
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g_buckZX_chk |= ( ui32SupplySrc &
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(AM_REG_PWRCTRL_DEVICEEN_PDM_M |
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AM_REG_PWRCTRL_DEVICEEN_UART1_M |
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AM_REG_PWRCTRL_DEVICEEN_UART0_M |
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AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_M |
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AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_M |
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AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_M |
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AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_M |
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AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_M |
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AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_M |
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AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_M) ) ?
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0x0 : CHKBUCKZX_DEVEN;
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//
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// If all 4 criteria were met, we're good to do the workaround.
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//
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return ( g_buckZX_chk ==
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(CHKBUCKZX_BUCKS | CHKBUCKZX_REV |
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CHKBUCKZX_TIMER | CHKBUCKZX_DEVEN) ) ? true : false;
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}
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//*****************************************************************************
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//
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// Set the buck zero cross settings to the values given.
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//
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// ui32Flags, one or more of the following:
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// SETBUCKZX_USE_PROVIDED_SETTINGS - Use the values provided in the parameters
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// to set the trim value(s).
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// SETBUCKZX_USE_SAVED_SETTINGS - Use the values that were previously saved
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// to set the trim value(s).
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// SETBUCKZX_SAVE_CURR_SETTINGS - Save the current trim values before
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// setting the new ones.
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// SETBUCKZX_RESTORE_CORE_ONLY - Restore the Core trim and save the current
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// value of the core buck trim iff
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// SETBUCKZX_SAVE_CURR_SETTINGS is set.
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// SETBUCKZX_RESTORE_MEM_ONLY - Restore the Mem trim and save the current
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// value of the mem buck trim iff
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// SETBUCKZX_SAVE_CURR_SETTINGS is set.
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// SETBUCKZX_RESTORE_BOTH - Restore both buck trims and save the
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// current value of both iff
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// SETBUCKZX_SAVE_CURR_SETTINGS is set.
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//
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//*****************************************************************************
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#define SETBUCKZX_USE_PROVIDED_SETTINGS 0x01
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#define SETBUCKZX_USE_SAVED_SETTINGS 0x02
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#define SETBUCKZX_SAVE_CURR_SETTINGS 0x04
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#define SETBUCKZX_RESTORE_CORE_ONLY 0x10
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#define SETBUCKZX_RESTORE_MEM_ONLY 0x20
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#define SETBUCKZX_RESTORE_BOTH ( SETBUCKZX_RESTORE_CORE_ONLY | \
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SETBUCKZX_RESTORE_MEM_ONLY )
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static void
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setBuckZX(uint32_t ui32CoreBuckZX, uint32_t ui32MemBuckZX, uint32_t ui32Flags)
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{
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uint32_t ui32SaveCore, ui32SaveMem, ui32NewCore, ui32NewMem;
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bool bDoRestore = false;
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//
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// Begin critical section.
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//
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AM_CRITICAL_BEGIN_ASM
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//
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// Get the current zero cross trim values.
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//
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ui32SaveCore = AM_BFR(MCUCTRL, BUCK3, COREBUCKZXTRIM);
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ui32SaveMem = AM_BFR(MCUCTRL, BUCK3, MEMBUCKZXTRIM);
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//
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// Determine which values will be restored.
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//
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if ( ui32Flags & SETBUCKZX_USE_SAVED_SETTINGS )
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{
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//
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// Use saved settings
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//
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ui32NewCore = g_ui32SaveCoreBuckZX;
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ui32NewMem = g_ui32SaveMemBuckZX;
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bDoRestore = true;
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}
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else if ( ui32Flags & SETBUCKZX_USE_PROVIDED_SETTINGS )
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{
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//
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// Use settings provided in the call parameters
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//
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ui32NewCore = ui32CoreBuckZX;
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ui32NewMem = ui32MemBuckZX;
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bDoRestore = true;
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}
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//
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// Restore the buck Core and Mem trim registers.
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//
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if ( bDoRestore )
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{
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if ( ui32Flags & SETBUCKZX_RESTORE_CORE_ONLY )
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{
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AM_BFW(MCUCTRL, BUCK3, COREBUCKZXTRIM, ui32NewCore);
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}
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if ( ui32Flags & SETBUCKZX_RESTORE_MEM_ONLY )
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{
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AM_BFW(MCUCTRL, BUCK3, MEMBUCKZXTRIM, ui32NewMem);
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}
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}
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if ( ui32Flags & SETBUCKZX_SAVE_CURR_SETTINGS )
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{
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//
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// Save off the zero cross values as read on entry to the function.
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//
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if ( ui32Flags & SETBUCKZX_RESTORE_CORE_ONLY )
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{
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g_ui32SaveCoreBuckZX = ui32SaveCore;
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}
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if ( ui32Flags & SETBUCKZX_RESTORE_MEM_ONLY )
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{
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g_ui32SaveMemBuckZX = ui32SaveMem;
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}
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}
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//
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// Done with critical section.
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//
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AM_CRITICAL_END_ASM
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}
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//*****************************************************************************
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//
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//! @brief Place the core into sleep or deepsleep.
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//!
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//! @param bSleepDeep - False for Normal or True Deep sleep.
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//!
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//! This function puts the MCU to sleep or deepsleep depending on bSleepDeep.
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//!
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//! Valid values for bSleepDeep are:
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//!
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//! AM_HAL_SYSCTRL_SLEEP_NORMAL
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//! AM_HAL_SYSCTRL_SLEEP_DEEP
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_sysctrl_sleep(bool bSleepDeep)
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{
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uint32_t ui32Critical;
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// uint32_t ui32DebugGpioSleep = g_ui32DebugGpioSleep - 1;
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bool bBuckZX_chk;
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volatile uint32_t ui32BuckTimer;
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//
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// Disable interrupts and save the previous interrupt state.
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//
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ui32Critical = am_hal_interrupt_master_disable();
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//
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// If the user selected DEEPSLEEP and the TPIU is off, attempt to enter
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// DEEP SLEEP.
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//
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if ((bSleepDeep == AM_HAL_SYSCTRL_SLEEP_DEEP) &&
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(AM_BFM(MCUCTRL, TPIUCTRL, ENABLE) == AM_REG_MCUCTRL_TPIUCTRL_ENABLE_DIS))
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{
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//
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// Prepare the core for deepsleep (write 1 to the DEEPSLEEP bit).
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//
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AM_BFW(SYSCTRL, SCR, SLEEPDEEP, 1);
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//
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// Check if special buck handling is needed
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//
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bBuckZX_chk = buckZX_chk();
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if ( bBuckZX_chk )
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{
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ui32BuckTimer = g_ui32BuckTimer - 1;
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//
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// Before going to sleep, clear the buck timers.
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// This will also handle the case where we're going back to
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// sleep before the buck sequence has even completed.
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//
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am_hal_ctimer_clear(ui32BuckTimer, AM_HAL_CTIMER_BOTH);
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//
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// Set CMPR0 of both timerA and timerB to the period value
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//
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#define TIMER_PERIOD_BUCKS 1
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am_hal_ctimer_period_set(ui32BuckTimer,
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AM_HAL_CTIMER_BOTH,
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TIMER_PERIOD_BUCKS |
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(TIMER_PERIOD_BUCKS << 16),
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0);
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//
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// Disable bucks before going to sleep.
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//
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am_hal_pwrctrl_bucks_disable();
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}
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//
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// Execute the sleep instruction.
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//
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AM_ASM_WFI;
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//
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// Return from sleep
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//
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if ( bBuckZX_chk )
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{
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//
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// Adjust the core and mem trims
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//
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setBuckZX(COREZXVALUE, MEMZXVALUE,
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SETBUCKZX_USE_PROVIDED_SETTINGS |
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SETBUCKZX_RESTORE_BOTH );
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//
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// Delay for 2us before enabling bucks.
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//
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am_hal_flash_delay( FLASH_CYCLES_US(2) );
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//
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// Turn on the bucks
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//
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am_hal_pwrctrl_bucks_enable();
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//
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// Get the actual timer number
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//
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ui32BuckTimer = g_ui32BuckTimer - 1;
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//
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// Initialize the complete flag
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//
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g_bBuckRestoreComplete = false;
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//
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// Initialize the input flags
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//
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g_ui32BuckInputs = 0;
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//
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// Delay for 5us to make sure we're receiving clean buck signals.
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//
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am_hal_flash_delay( FLASH_CYCLES_US(5) );
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//
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// Start timers (set the enable bit, clear the clear bit)
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//
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am_hal_ctimer_start(ui32BuckTimer, AM_HAL_CTIMER_BOTH);
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}
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else
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{
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//
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// Since we're not doing anything, we're done, so set the done flag.
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//
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g_bBuckRestoreComplete = true;
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}
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}
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else
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{
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//
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// Prepare the core for normal sleep (write 0 to the DEEPSLEEP bit).
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//
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AM_BFW(SYSCTRL, SCR, SLEEPDEEP, 0);
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//
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// Go to sleep.
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//
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AM_ASM_WFI;
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}
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//
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// Restore the interrupt state.
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//
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am_hal_interrupt_master_set(ui32Critical);
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}
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|
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//*****************************************************************************
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//
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//! @brief Enable the floating point module.
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//!
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//! Call this function to enable the ARM hardware floating point module.
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_sysctrl_fpu_enable(void)
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{
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//
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// Enable access to the FPU in both privileged and user modes.
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// NOTE: Write 0s to all reserved fields in this register.
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//
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AM_REG(SYSCTRL, CPACR) = (AM_REG_SYSCTRL_CPACR_CP11(0x3) |
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AM_REG_SYSCTRL_CPACR_CP10(0x3));
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}
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|
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//*****************************************************************************
|
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//
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//! @brief Disable the floating point module.
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//!
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//! Call this function to disable the ARM hardware floating point module.
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//!
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//! @return None.
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//
|
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//*****************************************************************************
|
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void
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am_hal_sysctrl_fpu_disable(void)
|
|
{
|
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//
|
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// Disable access to the FPU in both privileged and user modes.
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// NOTE: Write 0s to all reserved fields in this register.
|
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//
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AM_REG(SYSCTRL, CPACR) = 0x00000000 &
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~(AM_REG_SYSCTRL_CPACR_CP11(0x3) |
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AM_REG_SYSCTRL_CPACR_CP10(0x3));
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}
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|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Enable stacking of FPU registers on exception entry.
|
|
//!
|
|
//! @param bLazy - Set to "true" to enable "lazy stacking".
|
|
//!
|
|
//! This function allows the core to save floating-point information to the
|
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//! stack on exception entry. Setting the bLazy option enables "lazy stacking"
|
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//! for interrupt handlers. Normally, mixing floating-point code and interrupt
|
|
//! driven routines causes increased interrupt latency, because the core must
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//! save extra information to the stack upon exception entry. With the lazy
|
|
//! stacking option enabled, the core will skip the saving of floating-point
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//! registers when possible, reducing average interrupt latency.
|
|
//!
|
|
//! @note This function should be called before the floating-point module is
|
|
//! used in interrupt-driven code. If it is not called, the core will not have
|
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//! any way to save context information for floating-point variables on
|
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//! exception entry.
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//!
|
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//! @return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
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am_hal_sysctrl_fpu_stacking_enable(bool bLazy)
|
|
{
|
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if ( bLazy )
|
|
{
|
|
//
|
|
// Enable automatic saving of FPU registers on exception entry, using lazy
|
|
// context saving.
|
|
//
|
|
AM_REG(SYSCTRL, FPCCR) |= (AM_REG_SYSCTRL_FPCCR_ASPEN(0x1) |
|
|
AM_REG_SYSCTRL_FPCCR_LSPEN(0x1));
|
|
}
|
|
else
|
|
{
|
|
//
|
|
// Enable automatic saving of FPU registers on exception entry.
|
|
//
|
|
AM_REG(SYSCTRL, FPCCR) |= AM_REG_SYSCTRL_FPCCR_ASPEN(0x1);
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Disable FPU register stacking on exception entry.
|
|
//!
|
|
//! This function disables all stacking of floating point registers for
|
|
//! interrupt handlers.
|
|
//!
|
|
//! @return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
am_hal_sysctrl_fpu_stacking_disable(void)
|
|
{
|
|
//
|
|
// Enable automatic saving of FPU registers on exception entry, using lazy
|
|
// context saving.
|
|
//
|
|
AM_REG(SYSCTRL, FPCCR) &= ~(AM_REG_SYSCTRL_FPCCR_ASPEN(0x1) |
|
|
AM_REG_SYSCTRL_FPCCR_LSPEN(0x1));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Issue a system wide reset using the AIRCR bit in the M4 system ctrl.
|
|
//!
|
|
//! This function issues a system wide reset (Apollo POR level reset).
|
|
//!
|
|
//! @return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
am_hal_sysctrl_aircr_reset(void)
|
|
{
|
|
//
|
|
// Set the system reset bit in the AIRCR register
|
|
//
|
|
AM_REG(SYSCTRL, AIRCR) = AM_REG_SYSCTRL_AIRCR_VECTKEY(0x5FA) |
|
|
AM_REG_SYSCTRL_AIRCR_SYSRESETREQ(1);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Buck CTimer ISR initializer.
|
|
//!
|
|
//! @param ui32BuckTimerNumber - Timer number to be used for handling the buck.
|
|
//! Must be 0-3.
|
|
//!
|
|
//! If called with an invalid timer (that is, not 0 - 3, or greater than
|
|
//! BUCK_TIMER_MAX), then the workaround will not be enabled.
|
|
//!
|
|
//! Instead, the bucks will be initialized with a value that will avoid the
|
|
//! issues described in the Errata (ERR019). However, this will cause a
|
|
//! less efficient energy usage condtion.
|
|
//!
|
|
//! @return 0.
|
|
//
|
|
//*****************************************************************************
|
|
uint32_t
|
|
am_hal_sysctrl_buck_ctimer_isr_init(uint32_t ui32BuckTimerNumber)
|
|
{
|
|
uint32_t ui32RetVal = 0;
|
|
|
|
//
|
|
// Initialize the input flags
|
|
//
|
|
g_ui32BuckInputs = 0;
|
|
|
|
//
|
|
// Initialize operation complete flag
|
|
//
|
|
g_bBuckRestoreComplete = false;
|
|
|
|
//
|
|
// Initialize to assume there is no valid timer.
|
|
//
|
|
g_ui32BuckTimer = 0;
|
|
|
|
if ( ui32BuckTimerNumber > BUCK_TIMER_MAX )
|
|
{
|
|
if ( ( ui32BuckTimerNumber & 0xFFFF0000 ) ==
|
|
AM_HAL_SYSCTRL_BUCK_CTIMER_ZX_CONSTANT )
|
|
{
|
|
//
|
|
// The caller is asking for the hard option, which changes the
|
|
// settings to the more noise-immune, if less efficient, settings.
|
|
// While we're at it, go ahead and save off the current settings.
|
|
//
|
|
if ( (ui32BuckTimerNumber & 0x0000FFFF) == 0 )
|
|
{
|
|
setBuckZX(COREZXVALUE, MEMZXVALUE,
|
|
SETBUCKZX_USE_PROVIDED_SETTINGS |
|
|
SETBUCKZX_SAVE_CURR_SETTINGS |
|
|
SETBUCKZX_RESTORE_BOTH );
|
|
}
|
|
else
|
|
{
|
|
uint32_t ui32Core, ui32Mem;
|
|
|
|
//
|
|
// Use the setting provided in the parameter.
|
|
//
|
|
ui32Core = (((ui32BuckTimerNumber & 0x001F) >> 0) - 1) & 0xF;
|
|
ui32Mem = (((ui32BuckTimerNumber & 0x1F00) >> 8) - 1) & 0xF;
|
|
|
|
setBuckZX(ui32Core, ui32Mem,
|
|
SETBUCKZX_USE_PROVIDED_SETTINGS |
|
|
SETBUCKZX_SAVE_CURR_SETTINGS |
|
|
SETBUCKZX_RESTORE_BOTH );
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
//
|
|
// Save off the current trim settings (but don't change any settings).
|
|
//
|
|
setBuckZX(0, 0, SETBUCKZX_SAVE_CURR_SETTINGS | SETBUCKZX_RESTORE_BOTH);
|
|
|
|
//
|
|
// The timer number will be maintained as (n + 1). Therefore, a value
|
|
// of 0 saved in the global is an invalid timer. 1=timer0, 2=timer1...
|
|
//
|
|
g_ui32BuckTimer = ui32BuckTimerNumber + 1;
|
|
|
|
//
|
|
// Register the timer ISRs
|
|
//
|
|
am_hal_ctimer_int_register( AM_HAL_CTIMER_INT_TIMERA0C0 <<
|
|
(ui32BuckTimerNumber * 2),
|
|
am_hal_sysctrl_buckA_ctimer_isr );
|
|
|
|
am_hal_ctimer_int_register( AM_HAL_CTIMER_INT_TIMERB0C0 <<
|
|
(ui32BuckTimerNumber * 2),
|
|
am_hal_sysctrl_buckB_ctimer_isr );
|
|
|
|
//
|
|
// Determine which timer input (A or B) is core buck and which is mem
|
|
// buck based on the timer number.
|
|
// For CTIMER 0 & 1: Timer A is mem buck, Timer B is core buck
|
|
// For CTIMER 2 & 3: Timer A is core buck, Timer B is mem buck
|
|
//
|
|
if ( (ui32BuckTimerNumber == 0) || (ui32BuckTimerNumber == 1) )
|
|
{
|
|
//
|
|
// Indicate that TimerB is core buck.
|
|
//
|
|
g_ui32CoreBuck = COREBUCK_TIMERB;
|
|
}
|
|
else
|
|
{
|
|
//
|
|
// Indicate that TimerA is core buck
|
|
//
|
|
g_ui32CoreBuck = COREBUCK_TIMERA;
|
|
}
|
|
|
|
//
|
|
// Clear and configure the timers
|
|
//
|
|
am_hal_ctimer_clear(ui32BuckTimerNumber, AM_HAL_CTIMER_BOTH);
|
|
|
|
am_hal_ctimer_config(ui32BuckTimerNumber,
|
|
(am_hal_ctimer_config_t*)&g_sBuckTimer);
|
|
|
|
//
|
|
// Enable the interrupts for timers A and B
|
|
//
|
|
am_hal_ctimer_int_enable( (AM_HAL_CTIMER_INT_TIMERA0C0 |
|
|
AM_HAL_CTIMER_INT_TIMERB0C0 ) <<
|
|
(ui32BuckTimerNumber * 2) );
|
|
|
|
//
|
|
// Enable the timer interrupt in the NVIC.
|
|
//
|
|
am_hal_interrupt_enable(AM_HAL_INTERRUPT_CTIMER);
|
|
}
|
|
|
|
return ui32RetVal;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Get buck update complete status.
|
|
//
|
|
//*****************************************************************************
|
|
bool
|
|
am_hal_sysctrl_buck_update_complete(void)
|
|
{
|
|
return g_bBuckRestoreComplete;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Buck CTIMER ISR (for handling buck switching via TimerA).
|
|
//
|
|
// Note: This handler assumes that the interrupt is cleared in am_ctimer_isr().
|
|
//
|
|
//*****************************************************************************
|
|
static void
|
|
am_hal_sysctrl_buckA_ctimer_isr(void)
|
|
{
|
|
//
|
|
// Begin critical section.
|
|
// Although a relatively long time, the following 2us delay is critically
|
|
// timed for re-trimming the buck and thus cannot be extended. Therefore,
|
|
// we must keep it inside the critical section.
|
|
//
|
|
AM_CRITICAL_BEGIN_ASM
|
|
|
|
//
|
|
// Delay for 2us.
|
|
//
|
|
am_hal_flash_delay( FLASH_CYCLES_US(2) );
|
|
|
|
//
|
|
// Determine which buck (core or mem) needs to be updated.
|
|
//
|
|
if ( g_ui32CoreBuck == COREBUCK_TIMERA )
|
|
{
|
|
//
|
|
// Timer A buck signal is the CORE buck.
|
|
// Restore the core buck.
|
|
//
|
|
setBuckZX(0, 0, SETBUCKZX_RESTORE_CORE_ONLY |
|
|
SETBUCKZX_USE_SAVED_SETTINGS );
|
|
}
|
|
else
|
|
{
|
|
//
|
|
// Timer A buck signal is the MEM buck.
|
|
// Restore the mem buck.
|
|
//
|
|
setBuckZX(0, 0, SETBUCKZX_RESTORE_MEM_ONLY |
|
|
SETBUCKZX_USE_SAVED_SETTINGS );
|
|
}
|
|
|
|
g_ui32BuckInputs |= 0x1;
|
|
|
|
if ( g_ui32BuckInputs == 0x3 )
|
|
{
|
|
g_bBuckRestoreComplete = true;
|
|
g_ui32BuckInputs = 0;
|
|
}
|
|
|
|
//
|
|
// End critical section.
|
|
//
|
|
AM_CRITICAL_END_ASM
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Buck CTIMER ISR (for handling buck switching via TimerB).
|
|
//
|
|
// Note: This handler assumes that the interrupt is cleared in am_ctimer_isr().
|
|
//
|
|
//*****************************************************************************
|
|
static void
|
|
am_hal_sysctrl_buckB_ctimer_isr(void)
|
|
{
|
|
//
|
|
// Begin critical section.
|
|
// Although a relatively long time, the following 2us delay is critically
|
|
// timed for re-trimming the buck and thus cannot be extended. Therefore,
|
|
// we must keep it inside the critical section.
|
|
//
|
|
AM_CRITICAL_BEGIN_ASM
|
|
|
|
//
|
|
// Delay for 2us.
|
|
//
|
|
am_hal_flash_delay( FLASH_CYCLES_US(2) );
|
|
|
|
//
|
|
// Determine which buck (core or mem) needs to be updated.
|
|
//
|
|
if ( g_ui32CoreBuck == COREBUCK_TIMERB )
|
|
{
|
|
//
|
|
// Timer B buck signal is the CORE buck.
|
|
// Restore the core buck.
|
|
//
|
|
setBuckZX(0, 0, SETBUCKZX_RESTORE_CORE_ONLY |
|
|
SETBUCKZX_USE_SAVED_SETTINGS );
|
|
}
|
|
else
|
|
{
|
|
//
|
|
// Timer B buck signal is the MEM buck.
|
|
// Restore the mem buck.
|
|
//
|
|
setBuckZX(0, 0, SETBUCKZX_RESTORE_MEM_ONLY |
|
|
SETBUCKZX_USE_SAVED_SETTINGS );
|
|
}
|
|
|
|
g_ui32BuckInputs |= 0x2;
|
|
|
|
if ( g_ui32BuckInputs == 0x3 )
|
|
{
|
|
g_bBuckRestoreComplete = true;
|
|
g_ui32BuckInputs = 0;
|
|
}
|
|
|
|
//
|
|
// End critical section.
|
|
//
|
|
AM_CRITICAL_END_ASM
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// End Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|