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https://github.com/RT-Thread/rt-thread.git
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55a2684e56
it can be worked in NORMAL or SIMPLE calling convention and in all the optimize level(none, low, medium, high) git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1691 bbd45198-f89e-11dd-88c7-29a3b14d5316
67 lines
1.7 KiB
NASM
67 lines
1.7 KiB
NASM
/*
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* File : context.asm
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-04-09 fify the first version
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* 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction
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* 2010-04-20 fify move peripheral ISR to bsp/interrupts.s34
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*
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* For : Renesas M16C
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* Toolchain : IAR's EW for M16C v3.401
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*/
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RSEG CSTACK
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RSEG ISTACK
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RSEG CODE(1)
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EXTERN rt_interrupt_from_thread
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EXTERN rt_interrupt_to_thread
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PUBLIC rt_hw_interrupt_disable
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PUBLIC rt_hw_interrupt_enable
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PUBLIC rt_hw_context_switch_to
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PUBLIC os_context_switch
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rt_hw_interrupt_disable:
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STC FLG, R0 ;fify 20100419
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FCLR I
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RTS
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rt_hw_interrupt_enable:
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LDC R0, FLG ;fify 20100419
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RTS
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.EVEN
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os_context_switch:
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PUSHM R0,R1,R2,R3,A0,A1,SB,FB
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MOV.W rt_interrupt_from_thread, A0
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STC ISP, [A0]
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MOV.W rt_interrupt_to_thread, A0
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LDC [A0], ISP
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POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack
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REIT ; Return from interrup
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/*
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* void rt_hw_context_switch_to(rt_uint32 to);
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* r0 --> to
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* this fucntion is used to perform the first thread switch
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*/
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rt_hw_context_switch_to:
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MOV.W R0, A0
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LDC [A0], ISP
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POPM R0,R1,R2,R3,A0,A1,SB,FB
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REIT
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END
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