252 lines
6.8 KiB
C
252 lines
6.8 KiB
C
/*
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* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-3-19 wangyq the first version
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* 2019-11-01 wangyq update libraries
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <drv_hwtimer.h>
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#include <board.h>
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#include <ald_cmu.h>
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#include <ald_timer.h>
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#ifdef RT_USING_HWTIMER
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struct es32f0_hwtimer_dev
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{
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rt_hwtimer_t parent;
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timer_handle_t *hwtimer_periph;
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IRQn_Type IRQn;
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};
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#ifdef BSP_USING_HWTIMER0
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static struct es32f0_hwtimer_dev hwtimer0;
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void BS16T0_Handler(void)
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{
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ald_timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE);
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rt_device_hwtimer_isr(&hwtimer0.parent);
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if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode)
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{
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ald_timer_base_stop(hwtimer0.hwtimer_periph);
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}
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}
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#endif
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#ifdef BSP_USING_HWTIMER1
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static struct es32f0_hwtimer_dev hwtimer1;
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void BS16T1_UART2_Handler(void)
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{
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if (ald_timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) &&
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ald_timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE))
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{
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ald_timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE);
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rt_device_hwtimer_isr(&hwtimer1.parent);
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if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode)
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{
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ald_timer_base_stop(hwtimer1.hwtimer_periph);
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}
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}
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}
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#endif
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#ifdef BSP_USING_HWTIMER2
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static struct es32f0_hwtimer_dev hwtimer2;
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void BS16T2_UART3_Handler(void)
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{
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if (ald_timer_get_it_status(hwtimer2.hwtimer_periph, TIMER_IT_UPDATE) &&
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ald_timer_get_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE))
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{
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ald_timer_clear_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE);
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rt_device_hwtimer_isr(&hwtimer2.parent);
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if (HWTIMER_MODE_ONESHOT == hwtimer2.parent.mode)
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{
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ald_timer_base_stop(hwtimer2.hwtimer_periph);
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}
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}
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}
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#endif
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#ifdef BSP_USING_HWTIMER3
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static struct es32f0_hwtimer_dev hwtimer3;
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/* can not use when DAC0 Handler is enabled */
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void BS16T3_DAC0_Handler(void)
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{
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/* if BS16T3 it */
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if (ald_timer_get_it_status(hwtimer3.hwtimer_periph, TIMER_IT_UPDATE) &&
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ald_timer_get_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE))
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{
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ald_timer_clear_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE);
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rt_device_hwtimer_isr(&hwtimer3.parent);
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if (HWTIMER_MODE_ONESHOT == hwtimer3.parent.mode)
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{
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ald_timer_base_stop(hwtimer3.hwtimer_periph);
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}
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}
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}
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#endif
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static struct rt_hwtimer_info es32f0_hwtimer_info =
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{
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48000000, /* maximum count frequency */
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1, /* minimum count frequency */
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65535, /* counter maximum value */
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HWTIMER_CNTMODE_UP
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};
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static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
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{
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struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
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RT_ASSERT(hwtimer != RT_NULL);
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if (1 == state)
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{
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ald_timer_base_init(hwtimer->hwtimer_periph);
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ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE);
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NVIC_EnableIRQ(hwtimer->IRQn);
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}
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hwtimer->parent.freq = ald_cmu_get_pclk1_clock();
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es32f0_hwtimer_info.maxfreq = ald_cmu_get_pclk1_clock();
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es32f0_hwtimer_info.minfreq = ald_cmu_get_pclk1_clock();
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}
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static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer,
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rt_uint32_t cnt,
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rt_hwtimer_mode_t mode)
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{
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struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
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RT_ASSERT(hwtimer != RT_NULL);
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WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt);
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ald_timer_base_start(hwtimer->hwtimer_periph);
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return RT_EOK;
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}
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static void es32f0_hwtimer_stop(rt_hwtimer_t *timer)
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{
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struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
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RT_ASSERT(hwtimer != RT_NULL);
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ald_timer_base_stop(hwtimer->hwtimer_periph);
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}
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static rt_uint32_t es32f0_hwtimer_count_get(rt_hwtimer_t *timer)
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{
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struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
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uint32_t hwtimer_count = 0;
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RT_ASSERT(hwtimer != RT_NULL);
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hwtimer_count = READ_REG(hwtimer->hwtimer_periph->perh->COUNT);
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return hwtimer_count;
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}
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static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer,
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rt_uint32_t cmd,
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void *args)
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{
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rt_err_t ret = RT_EOK;
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rt_uint32_t freq = 0;
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struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
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RT_ASSERT(hwtimer != RT_NULL);
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switch (cmd)
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{
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case HWTIMER_CTRL_FREQ_SET:
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freq = *(rt_uint32_t *)args;
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if (freq != ald_cmu_get_pclk1_clock())
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{
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ret = -RT_ERROR;
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}
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break;
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case HWTIMER_CTRL_STOP:
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ald_timer_base_stop(hwtimer->hwtimer_periph);
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break;
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default:
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ret = RT_EINVAL;
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break;
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}
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return ret;
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}
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static struct rt_hwtimer_ops es32f0_hwtimer_ops =
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{
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es32f0_hwtimer_init,
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es32f0_hwtimer_start,
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es32f0_hwtimer_stop,
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es32f0_hwtimer_count_get,
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es32f0_hwtimer_control
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};
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int rt_hw_hwtimer_init(void)
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{
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rt_err_t ret = RT_EOK;
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#ifdef BSP_USING_HWTIMER0
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static timer_handle_t _hwtimer_periph0;
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_hwtimer_periph0.perh = BS16T0;
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hwtimer0.IRQn = BS16T0_IRQn;
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hwtimer0.hwtimer_periph = &_hwtimer_periph0;
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hwtimer0.parent.info = &es32f0_hwtimer_info;
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hwtimer0.parent.ops = &es32f0_hwtimer_ops;
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ret = rt_device_hwtimer_register(&hwtimer0.parent, "timer0", &hwtimer0);
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#endif
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#ifdef BSP_USING_HWTIMER1
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static timer_handle_t _hwtimer_periph1;
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_hwtimer_periph1.perh = BS16T1;
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hwtimer1.IRQn = BS16T1_UART2_IRQn;
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hwtimer1.hwtimer_periph = &_hwtimer_periph1;
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hwtimer1.parent.info = &es32f0_hwtimer_info;
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hwtimer1.parent.ops = &es32f0_hwtimer_ops;
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ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1);
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#endif
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#ifdef BSP_USING_HWTIMER2
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static timer_handle_t _hwtimer_periph2;
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_hwtimer_periph2.perh = BS16T2;
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hwtimer2.IRQn = BS16T2_UART3_IRQn;
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hwtimer2.hwtimer_periph = &_hwtimer_periph2;
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hwtimer2.parent.info = &es32f0_hwtimer_info;
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hwtimer2.parent.ops = &es32f0_hwtimer_ops;
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ret = rt_device_hwtimer_register(&hwtimer2.parent, "timer2", &hwtimer2);
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#endif
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#ifdef BSP_USING_HWTIMER3
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static timer_handle_t _hwtimer_periph3;
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_hwtimer_periph3.perh = BS16T3;
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hwtimer3.IRQn = BS16T3_DAC0_IRQn;
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hwtimer3.hwtimer_periph = &_hwtimer_periph3;
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hwtimer3.parent.info = &es32f0_hwtimer_info;
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hwtimer3.parent.ops = &es32f0_hwtimer_ops;
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ret = rt_device_hwtimer_register(&hwtimer3.parent, "timer3", &hwtimer3);
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#endif
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return ret;
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}
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INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
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#endif
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