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ea6d73f140
1. Upgrade Cortex driver library (CMSIS -> CMSIS & Device): version 2.3.2 -> 3.0.1 & 3.0.0 - Remove "bsp/efm32/Libraries/CMSIS/Lib/ARM", "bsp/efm32/Libraries/CMSIS/Lib/G++" and "bsp/efm32/Libraries/CMSIS/SVD" to save space 2. Upgrade EFM32 driver libraries (efm32lib -> emlib): version 2.3.2 -> 3.0.0 - Remove "bsp/efm32/Libraries/Device/EnergyMicro/EFM32LG" and "bsp/efm32/Libraries/Device/EnergyMicro/EFM32TG" to save space 3. Upgrade EFM32GG_DK3750 development kit driver library: version 1.2.2 -> 2.0.1 4. Upgrade EFM32_Gxxx_DK development kit driver library: version 1.7.3 -> 2.0.1 5. Add energy management unit driver and test code 6. Modify linker script and related code to compatible with new version of libraries 7. Change EFM32 branch version number to 1.0 8. Add photo frame demo application git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2122 bbd45198-f89e-11dd-88c7-29a3b14d5316
460 lines
17 KiB
C
460 lines
17 KiB
C
/***************************************************************************//**
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* @file
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* @brief Pulse Counter (PCNT) peripheral API
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* @author Energy Micro AS
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* @version 3.0.0
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*******************************************************************************
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* @section License
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* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
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*******************************************************************************
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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* obligation to support this Software. Energy Micro AS is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Energy Micro AS will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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******************************************************************************/
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#ifndef __EM_PCNT_H
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#define __EM_PCNT_H
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#include <stdbool.h>
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#include "em_part.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************************************************************//**
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* @addtogroup EM_Library
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @addtogroup PCNT
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* @{
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******************************************************************************/
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/*******************************************************************************
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******************************** ENUMS ************************************
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******************************************************************************/
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/** Mode selection. */
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typedef enum
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{
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/** Disable pulse counter. */
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pcntModeDisable = _PCNT_CTRL_MODE_DISABLE,
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/** Single input LFACLK oversampling mode (available in EM0-EM2). */
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pcntModeOvsSingle = _PCNT_CTRL_MODE_OVSSINGLE,
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/** Externally clocked single input counter mode (available in EM0-EM3). */
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pcntModeExtSingle = _PCNT_CTRL_MODE_EXTCLKSINGLE,
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/** Externally clocked quadrature decoder mode (available in EM0-EM3). */
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pcntModeExtQuad = _PCNT_CTRL_MODE_EXTCLKQUAD
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} PCNT_Mode_TypeDef;
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#if (defined (_EFM32_TINY_FAMILY) || defined (_EFM32_GIANT_FAMILY))
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/** Counter event selection.
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* Note: unshifted values are being used for enumeration because multiple
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* configuration structure members use this type definition. */
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typedef enum
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{
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/** Counts up on up-count and down on down-count events. */
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pcntCntEventBoth = _PCNT_CTRL_CNTEV_BOTH,
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/** Only counts up on up-count events. */
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pcntCntEventUp = _PCNT_CTRL_CNTEV_UP,
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/** Only counts down on down-count events. */
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pcntCntEventDown = _PCNT_CTRL_CNTEV_DOWN,
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/** Never counts. */
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pcntCntEventNone = _PCNT_CTRL_CNTEV_NONE
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} PCNT_CntEvent_TypeDef;
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/** PRS sources for @p s0PRS and @p s1PRS. */
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typedef enum
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{
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pcntPRSCh0 = 0, /**< PRS channel 0. */
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pcntPRSCh1 = 1, /**< PRS channel 1. */
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pcntPRSCh2 = 2, /**< PRS channel 2. */
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pcntPRSCh3 = 3, /**< PRS channel 3. */
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pcntPRSCh4 = 4, /**< PRS channel 4. */
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pcntPRSCh5 = 5, /**< PRS channel 5. */
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pcntPRSCh6 = 6, /**< PRS channel 6. */
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pcntPRSCh7 = 7 /**< PRS channel 7. */
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} PCNT_PRSSel_TypeDef;
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/** PRS inputs of PCNT. */
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typedef enum
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{
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pcntPRSInputS0 = 0, /** PRS input 0. */
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pcntPRSInputS1 = 1 /** PRS input 1. */
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} PCNT_PRSInput_TypeDef;
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#endif
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/*******************************************************************************
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******************************* STRUCTS ***********************************
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******************************************************************************/
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/** Init structure. */
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typedef struct
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{
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/** Mode to operate in. */
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PCNT_Mode_TypeDef mode;
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/** Initial counter value (refer to reference manual for max value allowed).
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* Only used for #pcntModeOvsSingle (and possibly #pcntModeDisable) modes.
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* If using #pcntModeExtSingle or #pcntModeExtQuad modes, the counter
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* value is reset to HW reset value. */
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uint32_t counter;
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/** Initial top value (refer to reference manual for max value allowed).
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* Only used for #pcntModeOvsSingle (and possibly #pcntModeDisable) modes.
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* If using #pcntModeExtSingle or #pcntModeExtQuad modes, the top
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* value is reset to HW reset value. */
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uint32_t top;
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/** Polarity of incoming edge.
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* @li #pcntModeExtSingle mode - if false, positive edges are counted,
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* otherwise negative edges.
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* @li #pcntModeExtQuad mode - if true, counting direction is inverted. */
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bool negEdge;
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/** Counting direction, only applicable for #pcntModeOvsSingle and
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* #pcntModeExtSingle modes. */
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bool countDown;
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/** Enable filter, only available in #pcntModeOvsSingle mode. */
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bool filter;
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#if (defined (_EFM32_TINY_FAMILY) || defined (_EFM32_GIANT_FAMILY))
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/** Set to true to enable hysteresis. When its enabled, the PCNT will always
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* overflow and underflow to TOP/2. */
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bool hyst;
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/** Set to true to enable S1 to determine the direction of counting in
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* OVSSINGLE or EXTCLKSINGLE modes.
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* When S1 is high, the count direction is given by CNTDIR, and when S1 is
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* low, the count direction is the opposite. */
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bool s1CntDir;
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/** Selects whether the regular counter responds to up-count events,
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* down-count events, both or none. */
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PCNT_CntEvent_TypeDef cntEvent;
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/** Selects whether the auxiliary counter responds to up-count events,
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* down-count events, both or none. */
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PCNT_CntEvent_TypeDef auxCntEvent;
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/** Select PRS channel as input to S0IN in PCNTx_INPUT register. */
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PCNT_PRSSel_TypeDef s0PRS;
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/** Select PRS channel as input to S1IN in PCNTx_INPUT register. */
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PCNT_PRSSel_TypeDef s1PRS;
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#endif
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} PCNT_Init_TypeDef;
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/** Default config for PCNT init structure. */
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#if defined (_EFM32_GECKO_FAMILY)
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#define PCNT_INIT_DEFAULT \
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{ pcntModeDisable, /* Disabled by default. */ \
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_PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \
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_PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \
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false, /* Use positive edge. */ \
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false, /* Up-counting. */ \
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false /* Filter disabled. */ \
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}
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#elif (defined (_EFM32_TINY_FAMILY) || defined (_EFM32_GIANT_FAMILY))
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#define PCNT_INIT_DEFAULT \
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{ pcntModeDisable, /* Disabled by default. */ \
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_PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \
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_PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \
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false, /* Use positive edge. */ \
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false, /* Up-counting. */ \
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false, /* Filter disabled. */ \
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false, /* Hysteresis disabled. */ \
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true, /* Counter direction is given by CNTDIR. */ \
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pcntCntEventUp, /* Regular counter counts up on upcount events. */ \
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pcntCntEventNone, /* Auxiliary counter doesn't respond to events. */ \
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pcntPRSCh0, /* PRS channel 0 selected as S0IN. */ \
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pcntPRSCh0 /* PRS channel 0 selected as S1IN. */ \
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}
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#endif
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/*******************************************************************************
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***************************** PROTOTYPES **********************************
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******************************************************************************/
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/***************************************************************************//**
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* @brief
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* Get pulse counter value.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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*
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* @return
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* Current pulse counter value.
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******************************************************************************/
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__STATIC_INLINE uint32_t PCNT_CounterGet(PCNT_TypeDef *pcnt)
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{
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return pcnt->CNT;
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}
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#if (defined (_EFM32_TINY_FAMILY) || defined (_EFM32_GIANT_FAMILY))
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/***************************************************************************//**
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* @brief
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* Get auxiliary counter value.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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*
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* @return
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* Current auxiliary counter value.
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******************************************************************************/
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__STATIC_INLINE uint32_t PCNT_AuxCounterGet(PCNT_TypeDef *pcnt)
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{
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return pcnt->AUXCNT;
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}
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#endif
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void PCNT_CounterReset(PCNT_TypeDef *pcnt);
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void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top);
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/***************************************************************************//**
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* @brief
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* Set counter value.
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*
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* @details
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* The pulse counter is disabled while changing counter value, and reenabled
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* (if originally enabled) when counter value has been set.
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*
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* @note
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* This function will stall until synchronization to low frequency domain is
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* completed. For that reason, it should normally not be used when using
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* an external clock to clock the PCNT module, since stall time may be
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* undefined in that case. The counter should normally only be set when
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* operating in (or about to enable) #pcntModeOvsSingle mode.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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*
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* @param[in] count
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* Value to set in counter register.
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******************************************************************************/
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__STATIC_INLINE void PCNT_CounterSet(PCNT_TypeDef *pcnt, uint32_t count)
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{
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PCNT_CounterTopSet(pcnt, count, pcnt->TOP);
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}
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void PCNT_Enable(PCNT_TypeDef *pcnt, PCNT_Mode_TypeDef mode);
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void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable);
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void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init);
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#if (defined (_EFM32_TINY_FAMILY) || defined (_EFM32_GIANT_FAMILY))
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void PCNT_PRSInputEnable(PCNT_TypeDef *pcnt,
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PCNT_PRSInput_TypeDef prsInput,
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bool enable);
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#endif
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/***************************************************************************//**
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* @brief
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* Clear one or more pending PCNT interrupts.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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*
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* @param[in] flags
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* Pending PCNT interrupt source to clear. Use a bitwise logic OR combination
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* of valid interrupt flags for the PCNT module (PCNT_IF_nnn).
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******************************************************************************/
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__STATIC_INLINE void PCNT_IntClear(PCNT_TypeDef *pcnt, uint32_t flags)
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{
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pcnt->IFC = flags;
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}
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/***************************************************************************//**
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* @brief
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* Disable one or more PCNT interrupts.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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*
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* @param[in] flags
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* PCNT interrupt sources to disable. Use a bitwise logic OR combination of
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* valid interrupt flags for the PCNT module (PCNT_IF_nnn).
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******************************************************************************/
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__STATIC_INLINE void PCNT_IntDisable(PCNT_TypeDef *pcnt, uint32_t flags)
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{
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pcnt->IEN &= ~(flags);
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}
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/***************************************************************************//**
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* @brief
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* Enable one or more PCNT interrupts.
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*
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* @note
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* Depending on the use, a pending interrupt may already be set prior to
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* enabling the interrupt. Consider using PCNT_IntClear() prior to enabling
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* if such a pending interrupt should be ignored.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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*
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* @param[in] flags
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* PCNT interrupt sources to enable. Use a bitwise logic OR combination of
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* valid interrupt flags for the PCNT module (PCNT_IF_nnn).
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******************************************************************************/
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__STATIC_INLINE void PCNT_IntEnable(PCNT_TypeDef *pcnt, uint32_t flags)
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{
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pcnt->IEN |= flags;
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}
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/***************************************************************************//**
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* @brief
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* Get pending PCNT interrupt flags.
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*
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* @note
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* The event bits are not cleared by the use of this function.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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*
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* @return
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* PCNT interrupt sources pending. A bitwise logic OR combination of valid
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* interrupt flags for the PCNT module (PCNT_IF_nnn).
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******************************************************************************/
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__STATIC_INLINE uint32_t PCNT_IntGet(PCNT_TypeDef *pcnt)
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{
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return pcnt->IF;
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}
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/***************************************************************************//**
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* @brief
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* Get enabled and pending PCNT interrupt flags.
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*
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* @details
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* Useful for handling more interrupt sources in the same interrupt handler.
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*
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* @note
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* The event bits are not cleared by the use of this function.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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*
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* @return
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* Pending and enabled PCNT interrupt sources.
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* The return value is the bitwise AND combination of
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* - the OR combination of enabled interrupt sources in PCNT_IEN_nnn
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* register (PCNT_IEN_nnn) and
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* - the OR combination of valid interrupt flags of the PCNT module
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* (PCNT_IF_nnn).
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******************************************************************************/
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__STATIC_INLINE uint32_t PCNT_IntGetEnabled(PCNT_TypeDef *pcnt)
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{
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uint32_t tmp = 0U;
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/* Store pcnt->IEN in temporary variable in order to define explicit order
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* of volatile accesses. */
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tmp = pcnt->IEN;
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/* Bitwise AND of pending and enabled interrupts */
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return pcnt->IF & tmp;
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}
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/***************************************************************************//**
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* @brief
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* Set one or more pending PCNT interrupts from SW.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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*
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* @param[in] flags
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* PCNT interrupt sources to set to pending. Use a bitwise logic OR combination
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* of valid interrupt flags for the PCNT module (PCNT_IF_nnn).
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******************************************************************************/
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__STATIC_INLINE void PCNT_IntSet(PCNT_TypeDef *pcnt, uint32_t flags)
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{
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pcnt->IFS = flags;
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}
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void PCNT_Reset(PCNT_TypeDef *pcnt);
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/***************************************************************************//**
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* @brief
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* Get pulse counter top buffer value.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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*
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* @return
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* Current pulse counter top buffer value.
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******************************************************************************/
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__STATIC_INLINE uint32_t PCNT_TopBufferGet(PCNT_TypeDef *pcnt)
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{
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return pcnt->TOPB;
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}
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void PCNT_TopBufferSet(PCNT_TypeDef *pcnt, uint32_t val);
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/***************************************************************************//**
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* @brief
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* Get pulse counter top value.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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*
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* @return
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* Current pulse counter top value.
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******************************************************************************/
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__STATIC_INLINE uint32_t PCNT_TopGet(PCNT_TypeDef *pcnt)
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{
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return pcnt->TOP;
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}
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void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val);
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/** @} (end addtogroup PCNT) */
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/** @} (end addtogroup EM_Library) */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __EM_PCNT_H */
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