114 lines
3.7 KiB
C
114 lines
3.7 KiB
C
/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-12-04 Jiaxun Yang Initial version
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*/
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#ifndef _MIPSSIM_DRV_UART_H__
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#define _MIPSSIM_DRV_UART_H__
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#include "mipssim.h"
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#include <rthw.h>
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/* UART registers */
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#define UART_DAT(base) HWREG8(base + 0x00)
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#define UART_IER(base) HWREG8(base + 0x01)
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#define UART_IIR(base) HWREG8(base + 0x02)
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#define UART_FCR(base) HWREG8(base + 0x02)
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#define UART_LCR(base) HWREG8(base + 0x03)
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#define UART_MCR(base) HWREG8(base + 0x04)
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#define UART_LSR(base) HWREG8(base + 0x05)
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#define UART_MSR(base) HWREG8(base + 0x06)
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#define UART_LSB(base) HWREG8(base + 0x00)
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#define UART_MSB(base) HWREG8(base + 0x01)
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/* interrupt enable register */
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#define IER_IRxE 0x1 /* 接收有效数据中断使能 */
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#define IER_ITxE 0x2 /* 传输保存寄存器为空中断使能 */
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#define IER_ILE 0x4 /* 接收器线路状态中断使能 */
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#define IER_IME 0x8 /* Modem状态中断使能 */
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/* interrupt identification register */
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#define IIR_IMASK 0xf /* mask */
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#define IIR_RXTOUT 0xc /* receive timeout */
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#define IIR_RLS 0x6 /* receive line status */
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#define IIR_RXRDY 0x4 /* receive ready */
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#define IIR_TXRDY 0x2 /* transmit ready */
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#define IIR_NOPEND 0x1 /* nothing */
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#define IIR_MLSC 0x0 /* modem status */
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#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
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/* fifo control register */
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#define FIFO_ENABLE 0x01 /* enable fifo */
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#define FIFO_RCV_RST 0x02 /* reset receive fifo */
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#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
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#define FIFO_DMA_MODE 0x08 /* enable dma mode */
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#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
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#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
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#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
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#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
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// 线路控制寄存器
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/* character format control register */
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#define CFCR_DLAB 0x80 /* divisor latch */
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#define CFCR_SBREAK 0x40 /* send break */
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#define CFCR_PZERO 0x30 /* zero parity */
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#define CFCR_PONE 0x20 /* one parity */
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#define CFCR_PEVEN 0x10 /* even parity */
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#define CFCR_PODD 0x00 /* odd parity */
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#define CFCR_PENAB 0x08 /* parity enable */
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#define CFCR_STOPB 0x04 /* 2 stop bits */
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#define CFCR_8BITS 0x03 /* 8 data bits */
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#define CFCR_7BITS 0x02 /* 7 data bits */
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#define CFCR_6BITS 0x01 /* 6 data bits */
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#define CFCR_5BITS 0x00 /* 5 data bits */
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/* modem control register */
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#define MCR_LOOPBACK 0x10 /* loopback */
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#define MCR_IENABLE 0x08 /* output 2 = int enable */
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#define MCR_DRS 0x04 /* output 1 = xxx */
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#define MCR_RTS 0x02 /* enable RTS */
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#define MCR_DTR 0x01 /* enable DTR */
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/* line status register */
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#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
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#define LSR_TSRE 0x40 /* transmitter empty */
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#define LSR_TXRDY 0x20 /* transmitter ready */
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#define LSR_BI 0x10 /* break detected */
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#define LSR_FE 0x08 /* framing error */
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#define LSR_PE 0x04 /* parity error */
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#define LSR_OE 0x02 /* overrun error */
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#define LSR_RXRDY 0x01 /* receiver ready */
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#define LSR_RCV_MASK 0x1f
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/* UART interrupt enable register value */
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#define UARTIER_IME (1 << 3)
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#define UARTIER_ILE (1 << 2)
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#define UARTIER_ITXE (1 << 1)
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#define UARTIER_IRXE (1 << 0)
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/* UART line control register value */
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#define UARTLCR_DLAB (1 << 7)
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#define UARTLCR_BCB (1 << 6)
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#define UARTLCR_SPB (1 << 5)
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#define UARTLCR_EPS (1 << 4)
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#define UARTLCR_PE (1 << 3)
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#define UARTLCR_SB (1 << 2)
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/* UART line status register value */
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#define UARTLSR_ERROR (1 << 7)
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#define UARTLSR_TE (1 << 6)
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#define UARTLSR_TFE (1 << 5)
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#define UARTLSR_BI (1 << 4)
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#define UARTLSR_FE (1 << 3)
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#define UARTLSR_PE (1 << 2)
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#define UARTLSR_OE (1 << 1)
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#define UARTLSR_DR (1 << 0)
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#endif |