291 lines
6.6 KiB
C
291 lines
6.6 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2011-01-13 weety first version
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*/
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#include <rtthread.h>
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#include "at91sam926x.h"
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static rt_list_t clocks;
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struct clk {
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char name[32];
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rt_uint32_t rate_hz;
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struct clk *parent;
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rt_list_t node;
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};
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static struct clk clk32k = {
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"clk32k",
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AT91_SLOW_CLOCK,
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RT_NULL,
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{RT_NULL, RT_NULL},
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};
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static struct clk main_clk = {
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"main",
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0,
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RT_NULL,
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{RT_NULL, RT_NULL},
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};
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static struct clk plla = {
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"plla",
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0,
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RT_NULL,
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{RT_NULL, RT_NULL},
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};
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static struct clk mck = {
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"mck",
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0,
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RT_NULL,
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{RT_NULL, RT_NULL},
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};
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static struct clk uhpck = {
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"uhpck",
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0,
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RT_NULL,
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{RT_NULL, RT_NULL},
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};
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static struct clk pllb = {
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"pllb",
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0,
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&main_clk,
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{RT_NULL, RT_NULL},
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};
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static struct clk udpck = {
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"udpck",
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0,
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&pllb,
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{RT_NULL, RT_NULL},
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};
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static struct clk *const standard_pmc_clocks[] = {
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/* four primary clocks */
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&clk32k,
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&main_clk,
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&plla,
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/* MCK */
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&mck
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};
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/* clocks cannot be de-registered no refcounting necessary */
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struct clk *clk_get(const char *id)
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{
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struct clk *clk;
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rt_list_t *list;
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for (list = (&clocks)->next; list != &clocks; list = list->next)
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{
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clk = (struct clk *)rt_list_entry(list, struct clk, node);
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if (rt_strcmp(id, clk->name) == 0)
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return clk;
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}
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return RT_NULL;
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}
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rt_uint32_t clk_get_rate(struct clk *clk)
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{
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rt_uint32_t flags;
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rt_uint32_t rate;
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for (;;) {
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rate = clk->rate_hz;
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if (rate || !clk->parent)
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break;
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clk = clk->parent;
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}
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return rate;
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}
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static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
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{
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unsigned mul, div;
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div = reg & 0xff;
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mul = (reg >> 16) & 0x7ff;
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if (div && mul) {
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freq /= div;
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freq *= mul + 1;
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} else
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freq = 0;
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return freq;
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}
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static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
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{
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unsigned i, div = 0, mul = 0, diff = 1 << 30;
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unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
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/* PLL output max 240 MHz (or 180 MHz per errata) */
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if (out_freq > 240000000)
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goto fail;
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for (i = 1; i < 256; i++) {
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int diff1;
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unsigned input, mul1;
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/*
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* PLL input between 1MHz and 32MHz per spec, but lower
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* frequences seem necessary in some cases so allow 100K.
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* Warning: some newer products need 2MHz min.
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*/
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input = main_freq / i;
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if (input < 100000)
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continue;
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if (input > 32000000)
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continue;
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mul1 = out_freq / input;
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if (mul1 > 2048)
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continue;
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if (mul1 < 2)
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goto fail;
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diff1 = out_freq - input * mul1;
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if (diff1 < 0)
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diff1 = -diff1;
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if (diff > diff1) {
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diff = diff1;
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div = i;
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mul = mul1;
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if (diff == 0)
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break;
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}
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}
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if (i == 256 && diff > (out_freq >> 5))
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goto fail;
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return ret | ((mul - 1) << 16) | div;
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fail:
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return 0;
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}
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static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
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{
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if (pll == &pllb && (reg & AT91_PMC_USB96M))
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return freq / 2;
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else
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return freq;
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}
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/* PLLB generated USB full speed clock init */
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static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock)
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{
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rt_uint32_t at91_pllb_usb_init;
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/*
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* USB clock init: choose 48 MHz PLLB value,
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* disable 48MHz clock during usb peripheral suspend.
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*
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* REVISIT: assumes MCK doesn't derive from PLLB!
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*/
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uhpck.parent = &pllb;
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at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
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pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
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at91_sys_write(AT91_CKGR_PLLBR, 0);
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udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
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uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
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}
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static struct clk *at91_css_to_clk(unsigned long css)
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{
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switch (css) {
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case AT91_PMC_CSS_SLOW:
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return &clk32k;
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case AT91_PMC_CSS_MAIN:
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return &main_clk;
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case AT91_PMC_CSS_PLLA:
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return &plla;
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case AT91_PMC_CSS_PLLB:
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return &pllb;
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}
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return RT_NULL;
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}
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#define false 0
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#define true 1
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int at91_clock_init(rt_uint32_t main_clock)
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{
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unsigned tmp, freq, mckr;
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int i;
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int pll_overclock = false;
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/*
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* When the bootloader initialized the main oscillator correctly,
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* there's no problem using the cycle counter. But if it didn't,
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* or when using oscillator bypass mode, we must be told the speed
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* of the main clock.
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*/
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if (!main_clock) {
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do {
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tmp = at91_sys_read(AT91_CKGR_MCFR);
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} while (!(tmp & AT91_PMC_MAINRDY));
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main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
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}
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main_clk.rate_hz = main_clock;
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/* report if PLLA is more than mildly overclocked */
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plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
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if (plla.rate_hz > 209000000)
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pll_overclock = true;
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if (pll_overclock)
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;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
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at91_pllb_usbfs_clock_init(main_clock);
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/*
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* MCK and CPU derive from one of those primary clocks.
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* For now, assume this parentage won't change.
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*/
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mckr = at91_sys_read(AT91_PMC_MCKR);
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mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
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freq = mck.parent->rate_hz;
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freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
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mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
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/* Register the PMC's standard clocks */
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rt_list_init(&clocks);
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for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
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rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
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rt_list_insert_after(&clocks, &pllb.node);
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rt_list_insert_after(&clocks, &uhpck.node);
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rt_list_insert_after(&clocks, &udpck.node);
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/* MCK and CPU clock are "always on" */
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//clk_enable(&mck);
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/*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
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freq / 1000000, (unsigned) mck.rate_hz / 1000000,
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(unsigned) main_clock / 1000000,
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((unsigned) main_clock % 1000000) / 1000);*///cause blocked
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return 0;
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}
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/**
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* @brief System Clock Configuration
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*/
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void rt_hw_clock_init(void)
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{
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at91_clock_init(18432000);
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}
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