758 lines
25 KiB
C
758 lines
25 KiB
C
/**********************************************************************
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* $Id$ lpc177x_8x_emc.c 2011-06-02
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*//**
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* @file lpc177x_8x_emc.c
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* @brief Contains all functions support for EMC firmware library
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* on LPC177x_8x
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* @version 1.0
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* @date 02. June. 2011
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2011, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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**********************************************************************/
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#include "lpc177x_8x_emc.h"
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#include "lpc177x_8x_clkpwr.h"
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#include "lpc177x_8x_pinsel.h"
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/*********************************************************************//**
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* @brief EMC initialize
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* @param[in] None
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* @return None
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**********************************************************************/
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void EMC_Init(void)
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{
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uint8_t i;
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/* Enable clock for EMC */
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// CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCEMC, ENABLE);
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// LPC_EMC->Control = 0x00000001;
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// LPC_EMC->Config = 0x00000000;
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LPC_SC->PCONP |= 0x00000800;
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LPC_SC->EMCDLYCTL = 0x00001010;
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LPC_EMC->Control = 0x00000001;
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LPC_EMC->Config = 0x00000000;
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/* Pin configuration:
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* P2.14 - /EMC_CS2
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* P2.15 - /EMC_CS3
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*
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* P2.16 - /EMC_CAS
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* P2.17 - /EMC_RAS
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* P2.18 - EMC_CLK[0]
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* P2.19 - EMC_CLK[1]
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*
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* P2.20 - EMC_DYCS0
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* P2.22 - EMC_DYCS1
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* P2.22 - EMC_DYCS2
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* P2.23 - EMC_DYCS3
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*
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* P2.24 - EMC_CKE0
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* P2.25 - EMC_CKE1
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* P2.26 - EMC_CKE2
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* P2.27 - EMC_CKE3
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*
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* P2.28 - EMC_DQM0
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* P2.29 - EMC_DQM1
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* P2.30 - EMC_DQM2
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* P2.31 - EMC_DQM3
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*
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* P3.0-P3.31 - EMC_D[0-31]
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* P4.0-P4.23 - EMC_A[0-23]
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*
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* P4.24 - /EMC_OE
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* P4.25 - /EMC_WE
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*
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* P4.30 - /EMC_CS0
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* P4.31 - /EMC_CS1
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*/
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PINSEL_ConfigPin(2,14,1);
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PINSEL_ConfigPin(2,15,1);
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PINSEL_ConfigPin(2,16,1);
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PINSEL_ConfigPin(2,17,1);
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PINSEL_ConfigPin(2,18,1);
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PINSEL_ConfigPin(2,19,1);
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PINSEL_ConfigPin(2,20,1);
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PINSEL_ConfigPin(2,21,1);
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PINSEL_ConfigPin(2,22,1);
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PINSEL_ConfigPin(2,23,1);
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PINSEL_ConfigPin(2,24,1);
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PINSEL_ConfigPin(2,25,1);
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PINSEL_ConfigPin(2,26,1);
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PINSEL_ConfigPin(2,27,1);
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PINSEL_ConfigPin(2,28,1);
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PINSEL_ConfigPin(2,29,1);
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PINSEL_ConfigPin(2,30,1);
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PINSEL_ConfigPin(2,31,1);
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PINSEL_ConfigPin(5,0,1);
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PINSEL_ConfigPin(5,1,1);
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for(i = 0; i < 32; i++)
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{
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PINSEL_ConfigPin(3,i,1);
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PINSEL_ConfigPin(4,i,1);
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}
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}
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/*********************************************************************//**
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* @brief Configure Little Endian/Big Endian mode for EMC
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* @param[in] endia_mode Endian mode, should be:
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* - EMC_LITTLE_ENDIAN_MODE: Little-endian mode
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* - EMC_BIG_ENDIAN_MODE : Big-endian mode
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* @return None
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**********************************************************************/
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void EMC_ConfigEndianMode(uint32_t endian_mode)
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{
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LPC_EMC->Config = ((LPC_EMC->Config & 0x01)|endian_mode) & EMC_Config_MASK;
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}
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/****************** Group of Dynamic control functions************************/
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/*********************************************************************//**
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* @brief Set the value for dynamic clock enable bit
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* @param[in] clock_enable clock enable mode, should be:
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* - 0: Clock enable of idle devices are deasserted to
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* save power
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* - 1: All clock enables are driven HIGH continuously
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* @return None
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**********************************************************************/
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void EMC_DynCtrlClockEnable(uint32_t clock_enable)
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{
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LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl) |clock_enable);
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}
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/*********************************************************************//**
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* @brief Set the value for dynamic memory clock control:
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* stops or runs continuously
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* @param[in] clock_control clock control mode, should be:
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* - 0: CLKOUT stops when all SDRAMs are idle and
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* during self-refresh mode
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* - 1: CLKOUT runs continuously
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* @return None
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**********************************************************************/
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void EMC_DynCtrlClockControl(int32_t clock_control)
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{
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uint32_t mask = ~(uint32_t)(2);
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LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl & mask) |clock_control);
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}
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/*********************************************************************//**
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* @brief Switch the Self-refresh mode between normal and self-refresh mode
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* @param[in] self_refresh_mode self refresh mode, should be:
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* - 0: Normal mode
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* - 1: Enter self-refresh mode
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* @return None
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**********************************************************************/
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void EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode)
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{
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uint32_t mask = ~(uint32_t)(4);
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LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl & mask) |self_refresh_mode);
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}
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/*********************************************************************//**
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* @brief Enable/disable CLKOUT
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* @param[in] MMC_val Memory clock control mode, should be:
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* - 0: CLKOUT enabled
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* - 1: CLKOUT disabled
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* @return None
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**********************************************************************/
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void EMC_DynCtrlMMC(uint32_t MMC_val)
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{
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uint32_t mask = ~(uint32_t)(_BIT(5));
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LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl & mask) |MMC_val);
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}
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/*********************************************************************//**
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* @brief Issue SDRAM command
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* @param[in] SDRAM_command Command mode, should be:
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* - 0x00: Issue SDRAM NORMAL operation command
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* - 0x01: Issue SDRAM MODE command
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* - 0x02: Issue SDRAM PALL (precharge all) command
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* - 0x03: Issue SRAM NOP (no operation) command
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* @return None
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**********************************************************************/
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void EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command)
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{
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uint32_t mask = ~(uint32_t)(_SBF(7,0x03));
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LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl & mask)|SDRAM_command);
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}
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/*********************************************************************//**
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* @brief Switch between Normal operation and deep sleep power mode
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* @param[in] Power_command Low-power SDRAM deep-sleep mode, should be:
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* - 0: Normal operation
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* - 1: Enter deep-sleep mode
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* @return None
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**********************************************************************/
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void EMC_DynCtrlPowerDownMode(uint32_t Power_command)
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{
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uint32_t mask = ~(uint32_t)(_BIT(13));
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LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl & mask)|Power_command);
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}
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/*********************************************************************//**
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* @brief Set the value of EMC dynamic memory registers
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* @param[in] par EMC register that will set value, should be:
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* - EMC_DYN_MEM_REFRESH_TIMER: Dynamic Refresh register
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* - EMC_DYN_MEM_READ_CONFIG: Dynamic Read Config register
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* - EMC_DYN_MEM_TRP: Dynamic RP register
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* - EMC_DYN_MEM_TRAS: Dynamic RAS register
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* - EMC_DYN_MEM_TSREX: Dynamic SREX register
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* - EMC_DYN_MEM_TAPR: Dynamic APR register
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* - EMC_DYN_MEM_TDAL: Dynamic DAL register
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* - EMC_DYN_MEM_TWR: Dynamic WR register
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* - EMC_DYN_MEM_TRC: Dynamic RC register
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* - EMC_DYN_MEM_TRFC: Dynamic RFC register
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* - EMC_DYN_MEM_TXSR: Dynamic XSR register
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* - EMC_DYN_MEM_TRRD: Dynamic RRD register
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* - EMC_DYN_MEM_TMRD: Dynamic MRD register
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* @return None
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**********************************************************************/
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void EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val)
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{
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switch ( par)
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{
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case EMC_DYN_MEM_REFRESH_TIMER:
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LPC_EMC->DynamicRefresh = val;
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break;
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case EMC_DYN_MEM_READ_CONFIG:
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LPC_EMC->DynamicReadConfig = val;
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break;
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case EMC_DYN_MEM_TRP:
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LPC_EMC->DynamicRP = val;
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break;
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case EMC_DYN_MEM_TRAS:
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LPC_EMC->DynamicRAS = val;
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break;
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case EMC_DYN_MEM_TSREX:
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LPC_EMC->DynamicSREX = val;
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break;
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case EMC_DYN_MEM_TAPR:
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LPC_EMC->DynamicAPR = val;
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break;
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case EMC_DYN_MEM_TDAL:
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LPC_EMC->DynamicDAL = val;
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break;
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case EMC_DYN_MEM_TWR:
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LPC_EMC->DynamicWR = val;
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break;
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case EMC_DYN_MEM_TRC:
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LPC_EMC->DynamicRC = val;
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break;
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case EMC_DYN_MEM_TRFC:
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LPC_EMC->DynamicRFC = val;
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break;
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case EMC_DYN_MEM_TXSR:
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LPC_EMC->DynamicXSR = val;
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break;
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case EMC_DYN_MEM_TRRD:
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LPC_EMC->DynamicRRD = val;
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break;
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case EMC_DYN_MEM_TMRD:
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LPC_EMC->DynamicMRD = val;
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break;
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}
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}
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/*********************************************************************//**
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* @brief Set extended wait time out for accessing static memory
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* @param[in] Extended_wait_time_out timeout value that will be set
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* @return None
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**********************************************************************/
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void EMC_StaticExtendedWait(uint32_t Extended_wait_time_out)
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{
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LPC_EMC->StaticExtendedWait = Extended_wait_time_out;
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}
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/*********************************************************************//**
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* @brief Configure the memory device
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* @param[in] index index number, should be from 0 to 3
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* @param[in] mem_dev Memory device, should be:
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* - 0x00: SDRAM
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* - 0x01: Low-power SDRAM
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* - 0x02: Micron Syncflash
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* @return None
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**********************************************************************/
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void EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev)
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{
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uint32_t mask = ~(uint32_t)(_SBF(3, 0x03));
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switch ( index)
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{
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case 0:
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LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | mem_dev;
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break;
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case 1:
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LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | mem_dev;
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break;
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case 2:
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LPC_EMC->DynamicConfig2 =(LPC_EMC->DynamicConfig2 & mask) | mem_dev;
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break;
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case 3:
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LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | mem_dev;
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break;
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}
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}
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/*********************************************************************//**
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* @brief Map the address for the memory device
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* @param[in] index index number, should be from 0 to 3
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* @param[in] add_mapped address where the memory will be mapped
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* @return None
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**********************************************************************/
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void EMC_DynMemConfigAM(uint32_t index , uint32_t add_mapped)
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{
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uint32_t mask = ~(uint32_t)(_SBF(7, 0x3f)) | ~(uint32_t)(_BIT(14)) ;
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switch ( index)
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{
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case 0:
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LPC_EMC->DynamicConfig0 = ( LPC_EMC->DynamicConfig0 & mask) | add_mapped;
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break;
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case 1:
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LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | add_mapped;
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break;
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case 2:
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LPC_EMC->DynamicConfig2 = (LPC_EMC->DynamicConfig2 & mask) | add_mapped;
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break;
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case 3:
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LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | add_mapped;
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break;
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}
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}
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/*********************************************************************//**
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* @brief Enable/disable the buffer
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* @param[in] index index number, should be from 0 to 3
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* @param[in] buff_control buffer control mode, should be:
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* - ENABLE
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* - DISABLE
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* @return None
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**********************************************************************/
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void EMC_DynMemConfigB(uint32_t index , uint32_t buff_control)
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{
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uint32_t mask = ~(uint32_t)(_BIT(19)) ;
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switch ( index)
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{
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case 0:
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LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | buff_control;
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break;
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case 1:
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LPC_EMC->DynamicConfig1 = ( LPC_EMC->DynamicConfig1 & mask) | buff_control;
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break;
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case 2:
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LPC_EMC->DynamicConfig2 = (LPC_EMC->DynamicConfig2 & mask)| buff_control;
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break;
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case 3:
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LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | buff_control;
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break;
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}
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}
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/*********************************************************************//**
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* @brief Configure write permission: protect or not
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* @param[in] index index number, should be from 0 to 3
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* @param[in] permission permission mode, should be:
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* - ENABLE: protect
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* - DISABLE: not protect
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* @return None
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**********************************************************************/
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void EMC_DynMemConfigP(uint32_t index , uint32_t permission)
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{
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uint32_t mask = ~(uint32_t)(_BIT(20)) ;
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switch ( index)
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{
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case 0:
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LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | permission;
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break;
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case 1:
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LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | permission;
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break;
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case 2:
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LPC_EMC->DynamicConfig2 = ( LPC_EMC->DynamicConfig2 & mask) | permission;
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break;
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case 3:
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LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | permission;
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break;
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}
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}
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/*********************************************************************//**
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* @brief Set value for RAS latency
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* @param[in] index index number, should be from 0 to 3
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* @param[in] ras_val RAS value should be in range: 0..3
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* @return None
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**********************************************************************/
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void EMC_DynMemRAS(uint32_t index , uint32_t ras_val)
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{
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uint32_t mask = ~(uint32_t)(0x03) ;
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switch ( index)
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{
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case 0:
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LPC_EMC->DynamicRasCas0 = (LPC_EMC->DynamicRasCas0 & mask) | ras_val;
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break;
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case 1:
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LPC_EMC->DynamicRasCas1 = (LPC_EMC->DynamicRasCas1 & mask) | ras_val;
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break;
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case 2:
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LPC_EMC->DynamicRasCas2 = (LPC_EMC->DynamicRasCas2 & mask) | ras_val;
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break;
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case 3:
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LPC_EMC->DynamicRasCas3 = (LPC_EMC->DynamicRasCas3 & mask) | ras_val;
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break;
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}
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}
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/*********************************************************************//**
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* @brief Set value for CAS latency
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* @param[in] index index number, should be from 0 to 3
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* @param[in] ras_val CAS value should be in range: 0..3
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* @return None
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**********************************************************************/
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void EMC_DynMemCAS(uint32_t index , uint32_t cas_val)
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{
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uint32_t mask = ~(uint32_t)(_SBF(8, 0x03)) ;
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switch ( index)
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{
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case 0:
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LPC_EMC->DynamicRasCas0 = (LPC_EMC->DynamicRasCas0 & mask) | cas_val;
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break;
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case 1:
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LPC_EMC->DynamicRasCas1 = (LPC_EMC->DynamicRasCas1 & mask) | cas_val;
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break;
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case 2:
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LPC_EMC->DynamicRasCas2 = (LPC_EMC->DynamicRasCas2 & mask )| cas_val;
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break;
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case 3:
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LPC_EMC->DynamicRasCas3 = ( LPC_EMC->DynamicRasCas3 & mask) | cas_val;
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break;
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}
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}
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/*********************************************************************//**
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* @brief Configure the memory width
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* @param[in] index index number, should be from 0 to 3
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* @param[in] mem_width memory width, should be:
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* - 0x00: 8-bits
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* - 0x01: 16-bits
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* - 0x02: 32-bits
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* @return None
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**********************************************************************/
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void EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width)
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{
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uint32_t mask = ~(uint32_t)(0x03) ;
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switch ( index)
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{
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case 0:
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LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | mem_width;
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break;
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case 1:
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LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | mem_width;
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break;
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case 2:
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LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask)| mem_width;
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break;
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case 3:
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LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | mem_width;
|
|
break;
|
|
}
|
|
}
|
|
/*********************************************************************//**
|
|
* @brief Configure the page mode
|
|
* @param[in] index index number, should be from 0 to 3
|
|
* @param[in] page_mode page mode, should be:
|
|
* - 0: disable
|
|
* - 1: asynchronous page mode enable
|
|
* @return None
|
|
**********************************************************************/
|
|
void EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode)
|
|
{
|
|
uint32_t mask = ~(uint32_t)(_BIT(3)) ;
|
|
switch ( index)
|
|
{
|
|
case 0:
|
|
LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | page_mode;
|
|
break;
|
|
case 1:
|
|
LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | page_mode;
|
|
break;
|
|
case 2:
|
|
LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask)| page_mode;
|
|
break;
|
|
case 3:
|
|
LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask)| page_mode;
|
|
break;
|
|
}
|
|
}
|
|
/*********************************************************************//**
|
|
* @brief Configure the chip select polarity
|
|
* @param[in] index index number, should be from 0 to 3
|
|
* @param[in] pagepol_val_mode page mode, should be:
|
|
* - 0: Active LOW ship select
|
|
* - 1: Active HIGH chip select
|
|
* @return None
|
|
**********************************************************************/
|
|
void EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val)
|
|
{
|
|
uint32_t mask = ~(uint32_t)(_BIT(6)) ;
|
|
switch ( index)
|
|
{
|
|
case 0:
|
|
LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | pol_val;
|
|
break;
|
|
case 1:
|
|
LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask)| pol_val;
|
|
break;
|
|
case 2:
|
|
LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | pol_val;
|
|
break;
|
|
case 3:
|
|
LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | pol_val;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*********************************************************************//**
|
|
* @brief Configure the byte lane state
|
|
* @param[in] index index number, should be from 0 to 3
|
|
* @param[in] pb_val Byte lane state, should be:
|
|
* - 0: For reads all bits in BLSn[3:0] are HIGH.
|
|
* - 1: For reads all bits in BLSn[3:0] are LOW.
|
|
* @return None
|
|
**********************************************************************/
|
|
void EMC_StaMemConfigPB(uint32_t index , uint32_t pb_val)
|
|
{
|
|
uint32_t mask = ~(uint32_t)(_BIT(7)) ;
|
|
switch ( index)
|
|
{
|
|
case 0:
|
|
LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask)| pb_val;
|
|
break;
|
|
case 1:
|
|
LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask)| pb_val;
|
|
break;
|
|
case 2:
|
|
LPC_EMC->StaticConfig2 =( LPC_EMC->StaticConfig2 & mask)| pb_val;
|
|
break;
|
|
case 3:
|
|
LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask)| pb_val;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*********************************************************************//**
|
|
* @brief Configure the extended wait value
|
|
* @param[in] index index number, should be from 0 to 3
|
|
* @param[in] ex_wait Extended wait mode, should be:
|
|
* - 0: Extended wait disabled.
|
|
* - 1: Extended wait enabled.
|
|
* @return None
|
|
**********************************************************************/
|
|
void EMC_StaMemConfigEW(uint32_t index , uint32_t ex_wait)
|
|
{
|
|
uint32_t mask = ~(uint32_t)(_BIT(8)) ;
|
|
switch ( index)
|
|
{
|
|
case 0:
|
|
LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | ex_wait;
|
|
break;
|
|
case 1:
|
|
LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | ex_wait;
|
|
break;
|
|
case 2:
|
|
LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | ex_wait;
|
|
break;
|
|
case 3:
|
|
LPC_EMC->StaticConfig3 =( LPC_EMC->StaticConfig3 & mask) | ex_wait;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*********************************************************************//**
|
|
* @brief Configure the buffer enable value
|
|
* @param[in] index index number, should be from 0 to 3
|
|
* @param[in] buf_val Buffer mode, should be:
|
|
* - 0: Buffer disabled.
|
|
* - 1: Buffer enabled.
|
|
* @return None
|
|
**********************************************************************/
|
|
void EMC_StaMemConfigB(uint32_t index , uint32_t buf_val)
|
|
{
|
|
uint32_t mask = ~(uint32_t)(_BIT(19)) ;
|
|
switch ( index)
|
|
{
|
|
case 0:
|
|
LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | buf_val;
|
|
break;
|
|
case 1:
|
|
LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | buf_val;
|
|
break;
|
|
case 2:
|
|
LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | buf_val;
|
|
break;
|
|
case 3:
|
|
LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | buf_val;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*********************************************************************//**
|
|
* @brief Configure the write permission
|
|
* @param[in] index index number, should be from 0 to 3
|
|
* @param[in] per_val Permission mode, should be:
|
|
* - 0: Write not protected.
|
|
* - 1: Write protected.
|
|
* @return None
|
|
**********************************************************************/
|
|
void EMC_StaMemConfigpP(uint32_t index , uint32_t per_val)
|
|
{
|
|
uint32_t mask = ~(uint32_t)(_BIT(20)) ;
|
|
switch ( index)
|
|
{
|
|
case 0:
|
|
LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | per_val;
|
|
break;
|
|
case 1:
|
|
LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | per_val;
|
|
break;
|
|
case 2:
|
|
LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | per_val;
|
|
break;
|
|
case 3:
|
|
LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | per_val;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*********************************************************************//**
|
|
* @brief Set the value of LPC_EMC static memory registers
|
|
* @param[in] index index number, should be from 0 to 3
|
|
* @param[in] EMC_STA_MEM_PAR Static register, should be:
|
|
* - EMC_STA_MEM_WAITWEN: StaticWaitWen0 register
|
|
* - EMC_STA_MEM_WAITOEN: StaticWaitOen0 register
|
|
* - EMC_STA_MEM_WAITRD: StaticWaitRd0 register
|
|
* - EMC_STA_MEM_WAITPAGE: StaticWaitPage0 register
|
|
* - EMC_STA_MEM_WAITWR: StaticWaitWr0 register
|
|
* - EMC_STA_MEM_WAITTURN: StaticWaitTurn0 register
|
|
* @return None
|
|
**********************************************************************/
|
|
void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val)
|
|
{
|
|
switch (index)
|
|
{
|
|
case 0:
|
|
switch ( par)
|
|
{
|
|
case EMC_STA_MEM_WAITWEN:
|
|
LPC_EMC->StaticWaitWen0 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITOEN:
|
|
LPC_EMC->StaticWaitOen0 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITRD:
|
|
LPC_EMC->StaticWaitRd0 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITPAGE:
|
|
LPC_EMC->StaticWaitPage0 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITWR:
|
|
LPC_EMC->StaticWaitWr0 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITTURN:
|
|
LPC_EMC->StaticWaitTurn0 = val;
|
|
break;
|
|
}
|
|
break;
|
|
case 1:
|
|
switch ( par)
|
|
{
|
|
case EMC_STA_MEM_WAITWEN:
|
|
LPC_EMC->StaticWaitWen1 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITOEN:
|
|
LPC_EMC->StaticWaitOen1 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITRD:
|
|
LPC_EMC->StaticWaitRd1 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITPAGE:
|
|
LPC_EMC->StaticWaitPage1 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITWR:
|
|
LPC_EMC->StaticWaitWr1 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITTURN:
|
|
LPC_EMC->StaticWaitTurn1 = val;
|
|
break;
|
|
}
|
|
break;
|
|
case 2:
|
|
switch ( par)
|
|
{
|
|
case EMC_STA_MEM_WAITWEN:
|
|
LPC_EMC->StaticWaitWen2 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITOEN:
|
|
LPC_EMC->StaticWaitOen2 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITRD:
|
|
LPC_EMC->StaticWaitRd2 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITPAGE:
|
|
LPC_EMC->StaticWaitPage2 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITWR:
|
|
LPC_EMC->StaticWaitWr2 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITTURN:
|
|
LPC_EMC->StaticWaitTurn2 = val;
|
|
break;
|
|
}
|
|
break;
|
|
case 3:
|
|
switch ( par)
|
|
{
|
|
case EMC_STA_MEM_WAITWEN:
|
|
LPC_EMC->StaticWaitWen3 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITOEN:
|
|
LPC_EMC->StaticWaitOen3 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITRD:
|
|
LPC_EMC->StaticWaitRd3 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITPAGE:
|
|
LPC_EMC->StaticWaitPage3 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITWR:
|
|
LPC_EMC->StaticWaitWr3 = val;
|
|
break;
|
|
case EMC_STA_MEM_WAITTURN:
|
|
LPC_EMC->StaticWaitTurn3 = val;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|