266 lines
11 KiB
C
266 lines
11 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FSL_FLEXBUS_H_
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#define _FSL_FLEXBUS_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup flexbus
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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#define FSL_FLEXBUS_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
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/*@}*/
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/*!
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* @brief Defines port size for FlexBus peripheral.
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*/
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typedef enum _flexbus_port_size
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{
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kFLEXBUS_4Bytes = 0x00U, /*!< 32-bit port size */
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kFLEXBUS_1Byte = 0x01U, /*!< 8-bit port size */
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kFLEXBUS_2Bytes = 0x02U /*!< 16-bit port size */
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} flexbus_port_size_t;
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/*!
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* @brief Defines number of cycles to hold address and attributes for FlexBus peripheral.
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*/
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typedef enum _flexbus_write_address_hold
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{
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kFLEXBUS_Hold1Cycle = 0x00U, /*!< Hold address and attributes one cycles after FB_CSn negates on writes */
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kFLEXBUS_Hold2Cycles = 0x01U, /*!< Hold address and attributes two cycles after FB_CSn negates on writes */
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kFLEXBUS_Hold3Cycles = 0x02U, /*!< Hold address and attributes three cycles after FB_CSn negates on writes */
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kFLEXBUS_Hold4Cycles = 0x03U /*!< Hold address and attributes four cycles after FB_CSn negates on writes */
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} flexbus_write_address_hold_t;
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/*!
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* @brief Defines number of cycles to hold address and attributes for FlexBus peripheral.
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*/
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typedef enum _flexbus_read_address_hold
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{
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kFLEXBUS_Hold1Or0Cycles = 0x00U, /*!< Hold address and attributes 1 or 0 cycles on reads */
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kFLEXBUS_Hold2Or1Cycles = 0x01U, /*!< Hold address and attributes 2 or 1 cycles on reads */
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kFLEXBUS_Hold3Or2Cycle = 0x02U, /*!< Hold address and attributes 3 or 2 cycles on reads */
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kFLEXBUS_Hold4Or3Cycle = 0x03U /*!< Hold address and attributes 4 or 3 cycles on reads */
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} flexbus_read_address_hold_t;
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/*!
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* @brief Address setup for FlexBus peripheral.
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*/
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typedef enum _flexbus_address_setup
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{
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kFLEXBUS_FirstRisingEdge = 0x00U, /*!< Assert FB_CSn on first rising clock edge after address is asserted */
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kFLEXBUS_SecondRisingEdge = 0x01U, /*!< Assert FB_CSn on second rising clock edge after address is asserted */
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kFLEXBUS_ThirdRisingEdge = 0x02U, /*!< Assert FB_CSn on third rising clock edge after address is asserted */
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kFLEXBUS_FourthRisingEdge = 0x03U, /*!< Assert FB_CSn on fourth rising clock edge after address is asserted */
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} flexbus_address_setup_t;
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/*!
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* @brief Defines byte-lane shift for FlexBus peripheral.
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*/
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typedef enum _flexbus_bytelane_shift
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{
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kFLEXBUS_NotShifted = 0x00U, /*!< Not shifted. Data is left-justified on FB_AD */
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kFLEXBUS_Shifted = 0x01U, /*!< Shifted. Data is right justified on FB_AD */
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} flexbus_bytelane_shift_t;
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/*!
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* @brief Defines multiplex group1 valid signals.
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*/
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typedef enum _flexbus_multiplex_group1_signal
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{
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kFLEXBUS_MultiplexGroup1_FB_ALE = 0x00U, /*!< FB_ALE */
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kFLEXBUS_MultiplexGroup1_FB_CS1 = 0x01U, /*!< FB_CS1 */
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kFLEXBUS_MultiplexGroup1_FB_TS = 0x02U, /*!< FB_TS */
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} flexbus_multiplex_group1_t;
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/*!
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* @brief Defines multiplex group2 valid signals.
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*/
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typedef enum _flexbus_multiplex_group2_signal
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{
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kFLEXBUS_MultiplexGroup2_FB_CS4 = 0x00U, /*!< FB_CS4 */
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kFLEXBUS_MultiplexGroup2_FB_TSIZ0 = 0x01U, /*!< FB_TSIZ0 */
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kFLEXBUS_MultiplexGroup2_FB_BE_31_24 = 0x02U, /*!< FB_BE_31_24 */
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} flexbus_multiplex_group2_t;
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/*!
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* @brief Defines multiplex group3 valid signals.
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*/
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typedef enum _flexbus_multiplex_group3_signal
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{
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kFLEXBUS_MultiplexGroup3_FB_CS5 = 0x00U, /*!< FB_CS5 */
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kFLEXBUS_MultiplexGroup3_FB_TSIZ1 = 0x01U, /*!< FB_TSIZ1 */
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kFLEXBUS_MultiplexGroup3_FB_BE_23_16 = 0x02U, /*!< FB_BE_23_16 */
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} flexbus_multiplex_group3_t;
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/*!
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* @brief Defines multiplex group4 valid signals.
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*/
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typedef enum _flexbus_multiplex_group4_signal
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{
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kFLEXBUS_MultiplexGroup4_FB_TBST = 0x00U, /*!< FB_TBST */
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kFLEXBUS_MultiplexGroup4_FB_CS2 = 0x01U, /*!< FB_CS2 */
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kFLEXBUS_MultiplexGroup4_FB_BE_15_8 = 0x02U, /*!< FB_BE_15_8 */
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} flexbus_multiplex_group4_t;
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/*!
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* @brief Defines multiplex group5 valid signals.
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*/
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typedef enum _flexbus_multiplex_group5_signal
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{
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kFLEXBUS_MultiplexGroup5_FB_TA = 0x00U, /*!< FB_TA */
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kFLEXBUS_MultiplexGroup5_FB_CS3 = 0x01U, /*!< FB_CS3 */
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kFLEXBUS_MultiplexGroup5_FB_BE_7_0 = 0x02U, /*!< FB_BE_7_0 */
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} flexbus_multiplex_group5_t;
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/*!
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* @brief Configuration structure that the user needs to set.
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*/
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typedef struct _flexbus_config
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{
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uint8_t chip; /*!< Chip FlexBus for validation */
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uint8_t waitStates; /*!< Value of wait states */
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uint32_t chipBaseAddress; /*!< Chip base address for using FlexBus */
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uint32_t chipBaseAddressMask; /*!< Chip base address mask */
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bool writeProtect; /*!< Write protected */
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bool burstWrite; /*!< Burst-Write enable */
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bool burstRead; /*!< Burst-Read enable */
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bool byteEnableMode; /*!< Byte-enable mode support */
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bool autoAcknowledge; /*!< Auto acknowledge setting */
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bool extendTransferAddress; /*!< Extend transfer start/extend address latch enable */
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bool secondaryWaitStates; /*!< Secondary wait states number */
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flexbus_port_size_t portSize; /*!< Port size of transfer */
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flexbus_bytelane_shift_t byteLaneShift; /*!< Byte-lane shift enable */
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flexbus_write_address_hold_t writeAddressHold; /*!< Write address hold or deselect option */
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flexbus_read_address_hold_t readAddressHold; /*!< Read address hold or deselect option */
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flexbus_address_setup_t addressSetup; /*!< Address setup setting */
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flexbus_multiplex_group1_t group1MultiplexControl; /*!< FlexBus Signal Group 1 Multiplex control */
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flexbus_multiplex_group2_t group2MultiplexControl; /*!< FlexBus Signal Group 2 Multiplex control */
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flexbus_multiplex_group3_t group3MultiplexControl; /*!< FlexBus Signal Group 3 Multiplex control */
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flexbus_multiplex_group4_t group4MultiplexControl; /*!< FlexBus Signal Group 4 Multiplex control */
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flexbus_multiplex_group5_t group5MultiplexControl; /*!< FlexBus Signal Group 5 Multiplex control */
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} flexbus_config_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus */
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/*!
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* @name FlexBus functional operation
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* @{
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*/
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/*!
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* @brief Initializes and configures the FlexBus module.
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*
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* This function enables the clock gate for FlexBus module.
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* Only chip 0 is validated and set to known values. Other chips are disabled.
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* Note that in this function, certain parameters, depending on external memories, must
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* be set before using the FLEXBUS_Init() function.
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* This example shows how to set up the uart_state_t and the
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* flexbus_config_t parameters and how to call the FLEXBUS_Init function by passing
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* in these parameters.
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@code
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flexbus_config_t flexbusConfig;
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FLEXBUS_GetDefaultConfig(&flexbusConfig);
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flexbusConfig.waitStates = 2U;
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flexbusConfig.chipBaseAddress = 0x60000000U;
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flexbusConfig.chipBaseAddressMask = 7U;
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FLEXBUS_Init(FB, &flexbusConfig);
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@endcode
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*
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* @param base FlexBus peripheral address.
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* @param config Pointer to the configuration structure
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*/
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void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config);
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/*!
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* @brief De-initializes a FlexBus instance.
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*
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* This function disables the clock gate of the FlexBus module clock.
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*
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* @param base FlexBus peripheral address.
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*/
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void FLEXBUS_Deinit(FB_Type *base);
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/*!
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* @brief Initializes the FlexBus configuration structure.
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*
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* This function initializes the FlexBus configuration structure to default value. The default
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* values are.
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@code
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fbConfig->chip = 0;
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fbConfig->writeProtect = 0;
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fbConfig->burstWrite = 0;
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fbConfig->burstRead = 0;
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fbConfig->byteEnableMode = 0;
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fbConfig->autoAcknowledge = true;
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fbConfig->extendTransferAddress = 0;
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fbConfig->secondaryWaitStates = 0;
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fbConfig->byteLaneShift = kFLEXBUS_NotShifted;
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fbConfig->writeAddressHold = kFLEXBUS_Hold1Cycle;
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fbConfig->readAddressHold = kFLEXBUS_Hold1Or0Cycles;
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fbConfig->addressSetup = kFLEXBUS_FirstRisingEdge;
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fbConfig->portSize = kFLEXBUS_1Byte;
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fbConfig->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE;
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fbConfig->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4 ;
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fbConfig->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5;
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fbConfig->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST;
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fbConfig->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA;
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@endcode
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* @param config Pointer to the initialization structure.
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* @see FLEXBUS_Init
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*/
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void FLEXBUS_GetDefaultConfig(flexbus_config_t *config);
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/*! @}*/
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus */
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/*! @}*/
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#endif /* _FSL_FLEXBUS_H_ */
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