141 lines
4.5 KiB
C
141 lines
4.5 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-04-16 bigmagic first version
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*/
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#ifndef __DRV_GPIO_H__
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#define __DRV_GPIO_H__
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "board.h"
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#include "interrupt.h"
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struct gpio_irq_def
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{
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void *irq_arg[32];
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void (*irq_cb[32])(void *param);
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rt_uint8_t irq_type[32];
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rt_uint8_t state[32];
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};
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#define GPIO_REG_GPFSEL0(BASE) HWREG32(BASE + 0x00)
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#define GPIO_REG_GPFSEL1(BASE) HWREG32(BASE + 0x04)
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#define GPIO_REG_GPFSEL2(BASE) HWREG32(BASE + 0x08)
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#define GPIO_REG_GPFSEL3(BASE) HWREG32(BASE + 0x0C)
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#define GPIO_REG_GPFSEL4(BASE) HWREG32(BASE + 0x10)
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#define GPIO_REG_GPFSEL5(BASE) HWREG32(BASE + 0x14)
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#define GPIO_REG_REV0(BASE) HWREG32(BASE + 0x18)
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#define GPIO_REG_GPSET0(BASE) HWREG32(BASE + 0x1C)
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#define GPIO_REG_GPSET1(BASE) HWREG32(BASE + 0x20)
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#define GPIO_REG_REV1(BASE) HWREG32(BASE + 0x24)
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#define GPIO_REG_GPCLR0(BASE) HWREG32(BASE + 0x28)
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#define GPIO_REG_GPCLR1(BASE) HWREG32(BASE + 0x2C)
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#define GPIO_REG_REV2(BASE) HWREG32(BASE + 0x30)
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#define GPIO_REG_GPLEV0(BASE) HWREG32(BASE + 0x34)
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#define GPIO_REG_GPLEV1(BASE) HWREG32(BASE + 0x38)
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#define GPIO_REG_REV3(BASE) HWREG32(BASE + 0x3C)
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#define GPIO_REG_GPEDS0(BASE) HWREG32(BASE + 0x40)
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#define GPIO_REG_GPEDS1(BASE) HWREG32(BASE + 0x44)
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#define GPIO_REG_REV4(BASE) HWREG32(BASE + 0x48)
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#define GPIO_REG_GPREN0(BASE) HWREG32(BASE + 0x4C)
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#define GPIO_REG_GPREN1(BASE) HWREG32(BASE + 0x50)
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#define GPIO_REG_REV5(BASE) HWREG32(BASE + 0x54)
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#define GPIO_REG_GPFEN0(BASE) HWREG32(BASE + 0x58)
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#define GPIO_REG_GPFEN1(BASE) HWREG32(BASE + 0x5C)
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#define GPIO_REG_REV6(BASE) HWREG32(BASE + 0x60)
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#define GPIO_REG_GPHEN0(BASE) HWREG32(BASE + 0x64)
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#define GPIO_REG_GPHEN1(BASE) HWREG32(BASE + 0x68)
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#define GPIO_REG_REV7(BASE) HWREG32(BASE + 0x6C)
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#define GPIO_REG_GPLEN0(BASE) HWREG32(BASE + 0x70)
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#define GPIO_REG_GPLEN1(BASE) HWREG32(BASE + 0x74)
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#define GPIO_REG_REV8(BASE) HWREG32(BASE + 0x78)
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#define GPIO_REG_GPAREN0(BASE) HWREG32(BASE + 0x7C)
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#define GPIO_REG_GPAREN1(BASE) HWREG32(BASE + 0x80)
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#define GPIO_REG_REV11(BASE) HWREG32(BASE + 0x84)
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#define GPIO_REG_GPAFEN0(BASE) HWREG32(BASE + 0x88)
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#define GPIO_REG_GPAFEN1(BASE) HWREG32(BASE + 0x8C)
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#define GPIO_REG_REV10(BASE) HWREG32(BASE + 0x90)
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#define GPIO_REG_GPPUD(BASE) HWREG32(BASE + 0x94)
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#define GPIO_REG_GPPUDCLK0(BASE) HWREG32(BASE + 0x98)
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#define GPIO_REG_GPPUDCLK1(BASE) HWREG32(BASE + 0x9C)
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#define GPIO_REG_REV9(BASE) HWREG32(BASE + 0xA0)
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#define GPIO_REG_TEST(BASE) HWREG32(BASE + 0xA4)
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#define GPIO_PUP_PDN_CNTRL_REG0(BASE) HWREG32(BASE + 0xE4)
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#define GPIO_PUP_PDN_CNTRL_REG1(BASE) HWREG32(BASE + 0xE8)
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#define GPIO_PUP_PDN_CNTRL_REG2(BASE) HWREG32(BASE + 0xEC)
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#define GPIO_PUP_PDN_CNTRL_REG3(BASE) HWREG32(BASE + 0xF0)
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typedef enum {
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GPIO_PIN_0,
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GPIO_PIN_1,
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GPIO_PIN_2,
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GPIO_PIN_3,
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GPIO_PIN_4,
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GPIO_PIN_5,
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GPIO_PIN_6,
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GPIO_PIN_7,
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GPIO_PIN_8,
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GPIO_PIN_9,
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GPIO_PIN_10,
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GPIO_PIN_11,
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GPIO_PIN_12,
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GPIO_PIN_13,
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GPIO_PIN_14,
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GPIO_PIN_15,
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GPIO_PIN_16,
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GPIO_PIN_17,
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GPIO_PIN_18,
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GPIO_PIN_19,
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GPIO_PIN_20,
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GPIO_PIN_21,
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GPIO_PIN_22,
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GPIO_PIN_23,
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GPIO_PIN_24,
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GPIO_PIN_25,
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GPIO_PIN_26,
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GPIO_PIN_27,
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GPIO_PIN_28,
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GPIO_PIN_29,
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GPIO_PIN_30,
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GPIO_PIN_31,
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GPIO_PIN_32,
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GPIO_PIN_33,
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GPIO_PIN_34,
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GPIO_PIN_35,
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GPIO_PIN_36,
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GPIO_PIN_37,
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GPIO_PIN_38,
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GPIO_PIN_39,
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GPIO_PIN_40,
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} GPIO_PIN;
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typedef enum {
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INPUT = 0b000,
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OUTPUT = 0b001,
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ALT0 = 0b100,
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ALT1 = 0b101,
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ALT2 = 0b110,
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ALT3 = 0b111,
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ALT4 = 0b011,
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ALT5 = 0b010
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} GPIO_FUNC;
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typedef enum {
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RASPI_NO_RESISTOR = 0x00,
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RASPI_PULL_UP = 0x01,
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RASPI_PULL_DOWN = 0x10
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} GPIO_PUPD_FUNC;
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void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode);
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void prev_raspi_pin_write(GPIO_PIN pin, int pin_value);
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int rt_hw_gpio_init(void);
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#endif /* __DRV_GPIO_H__ */
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