83 lines
1.9 KiB
C
83 lines
1.9 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2006-03-13 Bernard first version
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* 2011-05-15 lgnq modified according bernard's implementaion.
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*/
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#ifndef __FM3_UART_H__
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#define __FM3_UART_H__
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#include <rtthread.h>
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#include "mb9bf506r.h"
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#define SMR_SOE 0x01U
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#define SMR_BDS 0x04U
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#define SMR_SBL 0x08U
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#define SMR_WUCR 0x10U
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#define SMR_MD_UART 0x00U
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#define SMR_MD_UART_MP 0x20U
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#define SMR_MD_SIO 0x40U
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#define SMR_MD_LIN 0x60U
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#define SMR_MD_I2C 0x80U
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#define SCR_TXE 0x01U
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#define SCR_RXE 0x02U
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#define SCR_TBIE 0x04U
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#define SCR_TIE 0x08U
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#define SCR_RIE 0x10U
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#define SCR_UPGL 0x80U
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#define SSR_TBI 0x01U
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#define SSR_TDRE 0x02U
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#define SSR_RDRF 0x04U
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#define SSR_ORE 0x08U
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#define SSR_FRE 0x10U
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#define SSR_PE 0x20U
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#define SSR_REC 0x80U
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#define ESCR_P 0x08U
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#define ESCR_PEN 0x10U
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#define ESCR_INV 0x20U
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#define ESCR_ESBL 0x40U
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#define ESCR_FLWEN 0x80U
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#define ESCR_DATABITS_8 0x00U
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#define ESCR_DATABITS_5 0x01U
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#define ESCR_DATABITS_6 0x02U
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#define ESCR_DATABITS_7 0x03U
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#define ESCR_DATABITS_9 0x04U
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#define FIFO_SIZE 16
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/*
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* Enable/DISABLE Interrupt Controller
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*/
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/* deviation from MISRA-C:2004 Rule 19.7 */
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#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n))
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#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n))
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struct uart03_device
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{
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FM3_MFS03_UART_TypeDef *uart_regs;
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/* irq number */
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IRQn_Type rx_irq;
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IRQn_Type tx_irq;
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};
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struct uart47_device
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{
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FM3_MFS47_UART_TypeDef *uart_regs;
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/* irq number */
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IRQn_Type rx_irq;
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IRQn_Type tx_irq;
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rt_uint8_t fifo_size;
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};
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void rt_hw_serial_init(void);
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#endif
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