506 lines
15 KiB
Plaintext
506 lines
15 KiB
Plaintext
/***************************************************************************//**
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* \file cy8c6xxa_cm4_dual.ld
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* \version 2.91
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*
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* Linker file for the GNU C compiler.
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*
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* The main purpose of the linker script is to describe how the sections in the
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* input files should be mapped into the output file, and to control the memory
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* layout of the output file.
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*
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* \note The entry point location is fixed and starts at 0x10000000. The valid
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* application image should be placed there.
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*
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* \note The linker files included with the PDL template projects must be generic
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* and handle all common use cases. Your project may not use every section
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* defined in the linker files. In that case you may see warnings during the
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* build process. In your project, you can simply comment out or remove the
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* relevant code in the linker file.
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*
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********************************************************************************
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* \copyright
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* Copyright 2016-2021 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*******************************************************************************/
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OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
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SEARCH_DIR(.)
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GROUP(-lgcc -lc -lnosys)
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ENTRY(Reset_Handler)
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/* The size of the stack section at the end of CM4 SRAM */
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STACK_SIZE = 0x1000;
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/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
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* More about CM0+ prebuilt images, see here:
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* https://github.com/cypresssemiconductorco/psoc6cm0p
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*/
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/* The size of the Cortex-M0+ application image at the start of FLASH */
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FLASH_CM0P_SIZE = 0x2000;
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/* Force symbol to be entered in the output file as an undefined symbol. Doing
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* this may, for example, trigger linking of additional modules from standard
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* libraries. You may list several symbols for each EXTERN, and you may use
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* EXTERN multiple times. This command has the same effect as the -u command-line
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* option.
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*/
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EXTERN(Reset_Handler)
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/* The MEMORY section below describes the location and size of blocks of memory in the target.
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* Use this section to specify the memory regions available for allocation.
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*/
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MEMORY
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{
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/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
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* You can change the memory allocation by editing the 'ram' and 'flash' regions.
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* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
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* Using this memory region for other purposes will lead to unexpected behavior.
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* Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
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* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
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*/
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ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0xFD800
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flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x200000
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/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
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* You can assign sections to this memory region for only one of the cores.
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* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
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* Therefore, repurposing this memory region will prevent such middleware from operation.
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*/
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em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
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/* The following regions define device specific memory regions and must not be changed. */
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sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
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sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
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sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
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sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
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sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
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xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
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efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
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}
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/* Library configurations */
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GROUP(libgcc.a libc.a libm.a libnosys.a)
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/* Linker script to place sections and symbol values. Should be used together
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* with other linker script that defines memory regions FLASH and RAM.
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* It references following symbols, which must be defined in code:
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* Reset_Handler : Entry of reset handler
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*
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* It defines following symbols, which code can use without definition:
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* __exidx_start
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* __exidx_end
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* __copy_table_start__
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* __copy_table_end__
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* __zero_table_start__
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* __zero_table_end__
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* __etext
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* __data_start__
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* __preinit_array_start
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* __preinit_array_end
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* __init_array_start
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* __init_array_end
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* __fini_array_start
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* __fini_array_end
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* __data_end__
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* __bss_start__
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* __bss_end__
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* __end__
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* end
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* __HeapLimit
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* __StackLimit
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* __StackTop
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* __stack
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* __Vectors_End
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* __Vectors_Size
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*/
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SECTIONS
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{
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/* Cortex-M0+ application flash image area */
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.cy_m0p_image ORIGIN(flash) :
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{
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. = ALIGN(4);
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__cy_m0p_code_start = . ;
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KEEP(*(.cy_m0p_image))
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__cy_m0p_code_end = . ;
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} > flash
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/* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
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ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
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/* Cortex-M4 application flash area */
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.text ORIGIN(flash) + FLASH_CM0P_SIZE :
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{
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. = ALIGN(4);
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__Vectors = . ;
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KEEP(*(.vectors))
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. = ALIGN(4);
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__Vectors_End = .;
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__Vectors_Size = __Vectors_End - __Vectors;
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__end__ = .;
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. = ALIGN(4);
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*(.text*)
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KEEP(*(.init))
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KEEP(*(.fini))
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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/* Read-only code (constants). */
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*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
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KEEP(*(.eh_frame*))
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} > flash
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > flash
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > flash
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__exidx_end = .;
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/* To copy multiple ROM to RAM sections,
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* uncomment .copy.table section and,
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* define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
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.copy.table :
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{
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. = ALIGN(4);
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__copy_table_start__ = .;
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/* Copy interrupt vectors from flash to RAM */
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LONG (__Vectors) /* From */
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LONG (__ram_vectors_start__) /* To */
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LONG (__Vectors_End - __Vectors) /* Size */
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/* Copy data section to RAM */
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LONG (__etext) /* From */
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LONG (__data_start__) /* To */
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LONG (__data_end__ - __data_start__) /* Size */
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__copy_table_end__ = .;
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} > flash
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/* setction information for finsh shell begin */
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FSymTab :
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{
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. = ALIGN(4);
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__fsymtab_start = .;
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KEEP(*(FSymTab))
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__fsymtab_end = .;
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} > flash
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VSymTab :
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{
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. = ALIGN(4);
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__vsymtab_start = .;
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KEEP(*(VSymTab))
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__vsymtab_end = .;
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} > flash
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/* section information for utest */
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UtestTcTab :
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{
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. = ALIGN(4);
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__rt_utest_tc_tab_start = .;
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KEEP(*(UtestTcTab))
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__rt_utest_tc_tab_end = .;
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}
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/* section information for at server */
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RtAtCmdTab :
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{
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. = ALIGN(4);
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__rtatcmdtab_start = .;
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KEEP(*(UtestTcTab))
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__rtatcmdtab_end = .;
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}
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/* section information for modules */
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RTMSymTab :
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{
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. = ALIGN(4);
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__rtmsymtab_start = .;
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KEEP(*(UtestTcTab))
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__rtmsymtab_end = .;
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}
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/* section information for initial. */
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rti_fn :
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{
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. = ALIGN(4);
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__rt_init_start = .;
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KEEP(*(SORT(.rti_fn*)))
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__rt_init_end = .;
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} > flash
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rti_fn :
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{
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. = ALIGN(4);
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PROVIDE(__ctors_start__ = .);
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array))
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__rt_init_end = .;
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PROVIDE(__ctors_end__ = .);
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} > flash
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init_array :
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{
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. = ALIGN(4);
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__ctors_start__ = .;
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KEEP(*(SORT(.init_array*)))
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__ctors_end__ = .;
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} > flash
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/* setction information for finsh shell end */
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/* To clear multiple BSS sections,
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* uncomment .zero.table section and,
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* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
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.zero.table :
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{
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. = ALIGN(4);
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__zero_table_start__ = .;
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LONG (__bss_start__)
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LONG (__bss_end__ - __bss_start__)
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__zero_table_end__ = .;
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} > flash
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__etext = . ;
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.ramVectors (NOLOAD) : ALIGN(8)
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{
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__ram_vectors_start__ = .;
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KEEP(*(.ram_vectors))
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__ram_vectors_end__ = .;
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} > ram
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.data __ram_vectors_end__ :
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{
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. = ALIGN(4);
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__data_start__ = .;
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*(vtable)
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*(.data*)
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. = ALIGN(4);
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/* preinit data */
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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. = ALIGN(4);
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/* init data */
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(4);
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/* finit data */
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE_HIDDEN (__fini_array_end = .);
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KEEP(*(.jcr*))
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. = ALIGN(4);
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KEEP(*(.cy_ramfunc*))
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. = ALIGN(4);
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__data_end__ = .;
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} > ram AT>flash
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/* Place variables in the section that should not be initialized during the
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* device startup.
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*/
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.noinit (NOLOAD) : ALIGN(8)
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{
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KEEP(*(.noinit))
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} > ram
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/* The uninitialized global or static variables are placed in this section.
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*
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* The NOLOAD attribute tells linker that .bss section does not consume
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* any space in the image. The NOLOAD attribute changes the .bss type to
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* NOBITS, and that makes linker to A) not allocate section in memory, and
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* A) put information to clear the section with all zeros during application
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* loading.
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*
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* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
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* This makes linker to A) allocate zeroed section in memory, and B) copy
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* this section to RAM during application loading.
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*/
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.bss (NOLOAD):
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{
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. = ALIGN(4);
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__bss_start__ = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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__bss_end__ = .;
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} > ram
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.heap (NOLOAD):
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{
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__HeapBase = .;
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__end__ = .;
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end = __end__;
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KEEP(*(.heap*))
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. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
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__HeapLimit = .;
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} > ram
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/* .stack_dummy section doesn't contains any symbols. It is only
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* used for linker to calculate size of stack sections, and assign
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* values to stack symbols later */
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.stack_dummy (NOLOAD):
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{
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KEEP(*(.stack*))
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} > ram
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/* Set stack top to end of RAM, and stack limit move down by
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* size of stack_dummy section */
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__StackTop = ORIGIN(ram) + LENGTH(ram);
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__StackLimit = __StackTop - SIZEOF(.stack_dummy);
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PROVIDE(__stack = __StackTop);
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/* Check if data + heap + stack exceeds RAM limit */
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ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
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/* Used for the digital signature of the secure application and the Bootloader SDK application.
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* The size of the section depends on the required data size. */
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.cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
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{
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KEEP(*(.cy_app_signature))
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} > flash
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/* Emulated EEPROM Flash area */
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.cy_em_eeprom :
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{
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KEEP(*(.cy_em_eeprom))
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} > em_eeprom
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/* Supervisory Flash: User data */
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.cy_sflash_user_data :
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{
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KEEP(*(.cy_sflash_user_data))
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} > sflash_user_data
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/* Supervisory Flash: Normal Access Restrictions (NAR) */
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.cy_sflash_nar :
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{
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KEEP(*(.cy_sflash_nar))
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} > sflash_nar
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/* Supervisory Flash: Public Key */
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.cy_sflash_public_key :
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{
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KEEP(*(.cy_sflash_public_key))
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} > sflash_public_key
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/* Supervisory Flash: Table of Content # 2 */
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.cy_toc_part2 :
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{
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KEEP(*(.cy_toc_part2))
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} > sflash_toc_2
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/* Supervisory Flash: Table of Content # 2 Copy */
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.cy_rtoc_part2 :
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{
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KEEP(*(.cy_rtoc_part2))
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} > sflash_rtoc_2
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/* Places the code in the Execute in Place (XIP) section. See the smif driver
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* documentation for details.
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*/
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cy_xip :
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{
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__cy_xip_start = .;
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KEEP(*(.cy_xip))
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__cy_xip_end = .;
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} > xip
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/* eFuse */
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.cy_efuse :
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{
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KEEP(*(.cy_efuse))
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} > efuse
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/* These sections are used for additional metadata (silicon revision,
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* Silicon/JTAG ID, etc.) storage.
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*/
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.cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
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}
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/* The following symbols used by the cymcuelftool. */
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/* Flash */
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__cy_memory_0_start = 0x10000000;
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__cy_memory_0_length = 0x00200000;
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__cy_memory_0_row_size = 0x200;
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/* Emulated EEPROM Flash area */
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__cy_memory_1_start = 0x14000000;
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__cy_memory_1_length = 0x8000;
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__cy_memory_1_row_size = 0x200;
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/* Supervisory Flash */
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__cy_memory_2_start = 0x16000000;
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__cy_memory_2_length = 0x8000;
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__cy_memory_2_row_size = 0x200;
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/* XIP */
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__cy_memory_3_start = 0x18000000;
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__cy_memory_3_length = 0x08000000;
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__cy_memory_3_row_size = 0x200;
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/* eFuse */
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__cy_memory_4_start = 0x90700000;
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__cy_memory_4_length = 0x100000;
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__cy_memory_4_row_size = 1;
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/* EOF */
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