183 lines
4.3 KiB
C
183 lines
4.3 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-05-05 jg1uaa the first version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include "board.h"
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#include "drv_uart.h"
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#define SYSCON_BASE 0x40048000
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#define MEMMAP HWREG32(SYSCON_BASE + 0x000)
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#define SYSPLLCTRL HWREG32(SYSCON_BASE + 0x008)
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#define SYSPLLSTAT HWREG32(SYSCON_BASE + 0x00c)
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#define SYSPLLCLKSEL HWREG32(SYSCON_BASE + 0x040)
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#define SYSPLLCLKUEN HWREG32(SYSCON_BASE + 0x044)
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#define MAINCLKSEL HWREG32(SYSCON_BASE + 0x070)
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#define MAINCLKUEN HWREG32(SYSCON_BASE + 0x074)
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#define AHBCLKCTRL HWREG32(SYSCON_BASE + 0x080)
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#define PDRUNCFG HWREG32(SYSCON_BASE + 0x238)
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#define SCB_BASE 0xe000e000
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#define SYST_CSR HWREG32(SCB_BASE + 0x010)
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#define SYST_RVR HWREG32(SCB_BASE + 0x014)
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#define NVIC_ISER HWREG32(SCB_BASE + 0x100)
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#define NVIC_ICER HWREG32(SCB_BASE + 0x180)
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#define NVIC_ISPR HWREG32(SCB_BASE + 0x200)
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#define NVIC_ICPR HWREG32(SCB_BASE + 0x280)
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#define NVIC_IPR(irqno) HWREG32(SCB_BASE + 0x400 + (((irqno) / 4) << 2))
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#define SCB_SHPR3 HWREG32(SCB_BASE + 0xd20)
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extern unsigned char __bss_end__[];
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extern unsigned char _ram_end[];
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/**
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* This is the timer interrupt service routine.
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*/
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void SysTick_Handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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void os_clock_init(void)
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{
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/* bump up system clock 12MHz to 48MHz, using IRC (internal RC) osc. */
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MAINCLKSEL = 0; // main clock: IRC @12MHz (default, for safety)
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MAINCLKUEN = 0;
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MAINCLKUEN = 1;
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PDRUNCFG &= ~0x80; // power up System PLL
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SYSPLLCLKSEL = 0; // PLL clock source: IRC osc
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SYSPLLCLKUEN = 0;
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SYSPLLCLKUEN = 1;
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SYSPLLCTRL = 0x23; // Fcco = 2 x P x FCLKOUT
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// 192MHz = 2 x 2 x 48MHz
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// M = FCLKOUT / FCLKIN
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// 4 = 48MHz / 12MHz
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while (!(SYSPLLSTAT & 1)); // wait for lock PLL
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MAINCLKSEL = 3; // main clock: system PLL
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MAINCLKUEN = 0;
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MAINCLKUEN = 1;
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AHBCLKCTRL |= (1 << 16); // power up IOCON
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}
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void SysTick_init(void)
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{
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rt_uint32_t shpr3;
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/* set SysTick interrupt priority */
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shpr3 = SCB_SHPR3;
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shpr3 &= ~0xff000000;
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shpr3 |= 0x40 << 24;
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SCB_SHPR3 = shpr3;
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/* start SysTick */
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SYST_CSR = 0x06; // Clock source:Core, SysTick Exception:enable
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SYST_RVR = (CPU_CLOCK / RT_TICK_PER_SECOND) - 1;
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SYST_CSR = 0x07; // Counter:enable
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}
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/**
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* This function initializes LPC1114 SoC.
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*/
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void rt_hw_board_init(void)
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{
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os_clock_init();
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/* init SysTick */
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SysTick_init();
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#ifdef RT_USING_HEAP
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/* initialize system heap */
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rt_system_heap_init((void *)&__bss_end__, (void *)&_ram_end);
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#endif
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/* initialize uart */
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rt_hw_uart_init();
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#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
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/* set console device */
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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}
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/**
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* Enable External Interrupt
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*/
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void NVIC_EnableIRQ(rt_int32_t irqno)
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{
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NVIC_ISER = 1UL << (irqno & 0x1f);
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}
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/**
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* Disable External Interrupt
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*/
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void NVIC_DisableIRQ(rt_int32_t irqno)
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{
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NVIC_ICER = 1UL << (irqno & 0x1f);
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}
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/**
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* Get Pending Interrupt
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* Different from CMSIS implementation,
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* returns zero/non-zero, not zero/one.
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*/
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rt_uint32_t NVIC_GetPendingIRQ(rt_int32_t irqno)
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{
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return NVIC_ISPR & (1UL << (irqno & 0x1f));
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}
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/**
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* Set Pending Interrupt
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*/
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void NVIC_SetPendingIRQ(rt_int32_t irqno)
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{
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NVIC_ISPR = 1UL << (irqno & 0x1f);
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}
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/**
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* Clear Pending Interrupt
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*/
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void NVIC_ClearPendingIRQ(rt_int32_t irqno)
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{
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NVIC_ICPR = 1UL << (irqno & 0x1f);
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}
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/**
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* Set Interrupt Priority
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* Different from CMSIS implementation,
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* this code supports only external (device specific) interrupt.
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*/
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void NVIC_SetPriority(rt_int32_t irqno, rt_uint32_t priority)
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{
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rt_uint32_t shift, ipr;
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shift = (irqno % 4) * 8;
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ipr = NVIC_IPR(irqno);
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ipr &= ~(0xffUL << shift);
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ipr |= (priority & 0xff) << shift;
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NVIC_IPR(irqno) = ipr;
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}
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