295 lines
7.8 KiB
C
295 lines
7.8 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2010-11-13 weety first version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include "dm36x.h"
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#define MAX_HANDLERS 64
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extern rt_uint32_t rt_interrupt_nest;
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struct rt_irq_desc irq_desc[MAX_HANDLERS];
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/* exception and interrupt handler table */
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rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrupt_flag;
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#define IRQ_BIT(irq) ((irq) & 0x1f)
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#define FIQ_REG0_OFFSET 0x0000
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#define FIQ_REG1_OFFSET 0x0004
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#define IRQ_REG0_OFFSET 0x0008
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#define IRQ_REG1_OFFSET 0x000C
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#define IRQ_ENT_REG0_OFFSET 0x0018
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#define IRQ_ENT_REG1_OFFSET 0x001C
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#define IRQ_INCTL_REG_OFFSET 0x0020
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#define IRQ_EABASE_REG_OFFSET 0x0024
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#define IRQ_INTPRI0_REG_OFFSET 0x0030
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#define IRQ_INTPRI7_REG_OFFSET 0x004C
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/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
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static const rt_uint8_t dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
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[IRQ_DM3XX_VPSSINT0] = 2,
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[IRQ_DM3XX_VPSSINT1] = 6,
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[IRQ_DM3XX_VPSSINT2] = 6,
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[IRQ_DM3XX_VPSSINT3] = 6,
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[IRQ_DM3XX_VPSSINT4] = 6,
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[IRQ_DM3XX_VPSSINT5] = 6,
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[IRQ_DM3XX_VPSSINT6] = 6,
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[IRQ_DM3XX_VPSSINT7] = 7,
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[IRQ_DM3XX_VPSSINT8] = 6,
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[IRQ_ASQINT] = 6,
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[IRQ_DM365_IMXINT0] = 6,
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[IRQ_DM3XX_IMCOPINT] = 6,
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[IRQ_USBINT] = 4,
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[IRQ_DM3XX_RTOINT] = 4,
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[IRQ_DM3XX_TINT5] = 7,
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[IRQ_DM3XX_TINT6] = 7,
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[IRQ_CCINT0] = 5, /* dma */
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[IRQ_DM3XX_SPINT1_0] = 5, /* dma */
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[IRQ_DM3XX_SPINT1_1] = 5, /* dma */
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[IRQ_DM3XX_SPINT2_0] = 5, /* dma */
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[IRQ_DM365_PSCINT] = 7,
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[IRQ_DM3XX_SPINT2_1] = 7,
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[IRQ_DM3XX_TINT7] = 4,
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[IRQ_DM3XX_SDIOINT0] = 7,
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[IRQ_DM365_MBXINT] = 7,
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[IRQ_DM365_MBRINT] = 7,
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[IRQ_DM3XX_MMCINT0] = 7,
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[IRQ_DM3XX_MMCINT1] = 7,
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[IRQ_DM3XX_PWMINT3] = 7,
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[IRQ_DM365_DDRINT] = 7,
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[IRQ_DM365_AEMIFINT] = 7,
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[IRQ_DM3XX_SDIOINT1] = 4,
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[IRQ_DM365_TINT0] = 2, /* clockevent */
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[IRQ_DM365_TINT1] = 2, /* clocksource */
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[IRQ_DM365_TINT2] = 7, /* DSP timer */
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[IRQ_DM365_TINT3] = 7, /* system tick */
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[IRQ_PWMINT0] = 7,
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[IRQ_PWMINT1] = 7,
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[IRQ_DM365_PWMINT2] = 7,
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[IRQ_DM365_IICINT] = 3,
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[IRQ_UARTINT0] = 3,
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[IRQ_UARTINT1] = 3,
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[IRQ_DM3XX_SPINT0_0] = 3,
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[IRQ_DM3XX_SPINT0_1] = 3,
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[IRQ_DM3XX_GPIO0] = 3,
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[IRQ_DM3XX_GPIO1] = 7,
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[IRQ_DM3XX_GPIO2] = 4,
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[IRQ_DM3XX_GPIO3] = 4,
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[IRQ_DM3XX_GPIO4] = 7,
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[IRQ_DM3XX_GPIO5] = 7,
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[IRQ_DM3XX_GPIO6] = 7,
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[IRQ_DM3XX_GPIO7] = 7,
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[IRQ_DM3XX_GPIO8] = 7,
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[IRQ_DM3XX_GPIO9] = 7,
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[IRQ_DM365_GPIO10] = 7,
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[IRQ_DM365_GPIO11] = 7,
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[IRQ_DM365_GPIO12] = 7,
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[IRQ_DM365_GPIO13] = 7,
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[IRQ_DM365_GPIO14] = 7,
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[IRQ_DM365_GPIO15] = 7,
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[IRQ_DM365_KEYINT] = 7,
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[IRQ_DM365_COMMTX] = 7,
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[IRQ_DM365_COMMRX] = 7,
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[IRQ_EMUINT] = 7,
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};
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static inline unsigned int davinci_irq_readl(int offset)
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{
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return davinci_readl(DAVINCI_ARM_INTC_BASE + offset);
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}
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static inline void davinci_irq_writel(unsigned long value, int offset)
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{
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davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset);
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}
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/**
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* @addtogroup DM36X
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*/
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/*@{*/
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rt_isr_handler_t rt_hw_interrupt_handle(int vector, void *param)
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{
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rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
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return RT_NULL;
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}
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/**
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* This function will initialize hardware interrupt
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*/
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void rt_hw_interrupt_init(void)
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{
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int i;
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register rt_uint32_t idx;
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const rt_uint8_t *priority;
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priority = dm365_default_priorities;
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/* Clear all interrupt requests */
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davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
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davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
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davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
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davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
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/* Disable all interrupts */
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davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
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davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
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/* Interrupts disabled immediately, IRQ entry reflects all */
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davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);
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/* we don't use the hardware vector table, just its entry addresses */
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davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);
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/* Clear all interrupt requests */
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davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
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davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
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davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
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davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
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for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
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unsigned j;
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rt_uint32_t pri;
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for (j = 0, pri = 0; j < 32; j += 4, priority++)
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pri |= (*priority & 0x07) << j;
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davinci_irq_writel(pri, i);
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}
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/* init exceptions table */
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for(idx=0; idx < MAX_HANDLERS; idx++)
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{
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irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
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irq_desc[idx].param = RT_NULL;
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#ifdef RT_USING_INTERRUPT_INFO
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rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
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irq_desc[idx].counter = 0;
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#endif
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}
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/* init interrupt nest, and context in thread sp */
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rt_interrupt_nest = 0;
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rt_interrupt_from_thread = 0;
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rt_interrupt_to_thread = 0;
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rt_thread_switch_interrupt_flag = 0;
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}
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/**
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* This function will mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_mask(int irq)
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{
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unsigned int mask;
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rt_uint32_t l;
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mask = 1 << IRQ_BIT(irq);
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if (irq > 31) {
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l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
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l &= ~mask;
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davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
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} else {
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l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
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l &= ~mask;
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davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
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}
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}
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/**
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* This function will un-mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_umask(int irq)
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{
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unsigned int mask;
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rt_uint32_t l;
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mask = 1 << IRQ_BIT(irq);
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if (irq > 31) {
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l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
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l |= mask;
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davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
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} else {
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l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
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l |= mask;
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davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
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}
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}
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/**
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* This function will install a interrupt service routine to a interrupt.
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* @param vector the interrupt number
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* @param handler the interrupt service routine to be installed
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* @param param the interrupt service function parameter
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* @param name the interrupt name
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* @return old handler
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*/
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rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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void *param, const char *name)
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{
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rt_isr_handler_t old_handler = RT_NULL;
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if(vector < MAX_HANDLERS)
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{
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old_handler = irq_desc[vector].handler;
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if (handler != RT_NULL)
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{
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irq_desc[vector].handler = (rt_isr_handler_t)handler;
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irq_desc[vector].param = param;
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#ifdef RT_USING_INTERRUPT_INFO
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rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
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irq_desc[vector].counter = 0;
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#endif
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}
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}
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return old_handler;
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}
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#ifdef RT_USING_FINSH
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#ifdef RT_USING_INTERRUPT_INFO
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void list_irq(void)
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{
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int irq;
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rt_kprintf("number\tcount\tname\n");
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for (irq = 0; irq < MAX_HANDLERS; irq++)
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{
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if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
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{
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rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
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}
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}
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}
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#include <finsh.h>
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FINSH_FUNCTION_EXPORT(list_irq, list system irq);
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#ifdef FINSH_USING_MSH
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int cmd_list_irq(int argc, char** argv)
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{
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list_irq();
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return 0;
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}
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MSH_CMD_EXPORT_ALIAS(cmd_list_irq, list_irq, list system irq);
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#endif
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#endif
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#endif
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/*@}*/
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