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2168ed8e7d
PCI/PCIe have better performance and more devices support, such as NVMe, GPU, Powerful NIC (Like RDMA). PCI/PCIe can access control by IOMMU that the virtualiztion and userspace driver will more safety. PCI/PCIe device could hot plugging, no design modifications SoC required, PCI/PCIe on Embedded SoC is popular now. We make a simple framework to support them. Feature Lists: 1.PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC. 2.MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC. 3.PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework. 4.Endpoint: a simple EP framework for PCI FPGA or NTB function. 5.OFW: we only support work on OFW SoC, ACPI support in the future maybe. Host controller: 1. Common PCI host controller on ECAM. 2. Generic PCI host controller on ECAM. Signed-off-by: GuEe-GUI <2991707448@qq.com>
70 lines
1.9 KiB
C
70 lines
1.9 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-24 GuEe-GUI first version
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*/
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#ifndef __RT_PCI_ECAM_H__
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#define __RT_PCI_ECAM_H__
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#include <drivers/pci.h>
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#include <drivers/ofw.h>
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#include <drivers/ofw_io.h>
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#include <drivers/platform.h>
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/*
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* Memory address shift values for the byte-level address that
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* can be used when accessing the PCI Express Configuration Space.
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*/
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/*
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* Enhanced Configuration Access Mechanism (ECAM)
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*
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* See PCI Express Base Specification, Revision 5.0, Version 1.0,
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* Section 7.2.2, Table 7-1, p. 677.
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*/
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#define PCIE_ECAM_BUS_SHIFT 20 /* Bus number */
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#define PCIE_ECAM_DEVFN_SHIFT 12 /* Device and Function number */
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#define PCIE_ECAM_BUS_MASK 0xff
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#define PCIE_ECAM_DEVFN_MASK 0xff
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#define PCIE_ECAM_REG_MASK 0xfff /* Limit offset to a maximum of 4K */
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#define PCIE_ECAM_BUS(x) (((x) & PCIE_ECAM_BUS_MASK) << PCIE_ECAM_BUS_SHIFT)
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#define PCIE_ECAM_DEVFN(x) (((x) & PCIE_ECAM_DEVFN_MASK) << PCIE_ECAM_DEVFN_SHIFT)
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#define PCIE_ECAM_REG(x) ((x) & PCIE_ECAM_REG_MASK)
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#define PCIE_ECAM_OFFSET(bus, devfn, where) \
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(PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEVFN(devfn) | PCIE_ECAM_REG(where))
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struct pci_ecam_ops
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{
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rt_uint32_t bus_shift;
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const struct rt_pci_ops pci_ops;
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};
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struct pci_ecam_config_window
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{
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rt_uint32_t *bus_range;
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rt_uint32_t bus_shift;
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void *win;
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void *priv;
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const struct pci_ecam_ops *ops;
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};
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/* Default ECAM ops */
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extern const struct pci_ecam_ops pci_generic_ecam_ops;
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void *pci_ecam_map(struct rt_pci_bus *bus, rt_uint32_t devfn, int where);
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struct pci_ecam_config_window *pci_ecam_create(struct rt_pci_host_bridge *host_bridge,
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const struct pci_ecam_ops *ops);
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rt_err_t pci_host_common_probe(struct rt_platform_device *pdev);
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rt_err_t pci_host_common_remove(struct rt_platform_device *pdev);
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#endif /* __RT_PCI_ECAM_H__ */
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