936 lines
35 KiB
C
936 lines
35 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_pwm.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.pwm"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get the instance from the base address
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*
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* @param base PWM peripheral base address
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*
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* @return The PWM module instance
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*/
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static uint32_t PWM_GetInstance(PWM_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to PWM bases for each instance. */
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static PWM_Type *const s_pwmBases[] = PWM_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to PWM clocks for each PWM submodule. */
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static const clock_ip_name_t s_pwmClocks[][FSL_FEATURE_PWM_SUBMODULE_COUNT] = PWM_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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/*!
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* brief Complement the variable of type uint16_t as needed
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*
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* This function can complement the variable of type uint16_t as needed.For example,
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* need to ask for the opposite of a positive integer.
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*
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* param value Parameters of type uint16_t
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*/
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static inline uint16_t PWM_GetComplementU16(uint16_t value)
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{
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return (~value + 1U);
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}
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static inline uint16_t dutyCycleToReloadValue(uint8_t dutyCyclePercent)
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{
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/* Rounding calculations to improve the accuracy of reloadValue */
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return ((65535U * dutyCyclePercent) + 50U) / 100U;
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}
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static uint32_t PWM_GetInstance(PWM_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_pwmBases); instance++)
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{
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if (s_pwmBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_pwmBases));
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return instance;
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}
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/*!
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* brief Ungates the PWM submodule clock and configures the peripheral for basic operation.
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*
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* note This API should be called at the beginning of the application using the PWM driver.
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*
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* param base PWM peripheral base address
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* param subModule PWM submodule to configure
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* param config Pointer to user's PWM config structure.
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*
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* return kStatus_Success means success; else failed.
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*/
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status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config)
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{
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assert(config);
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uint16_t reg;
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/* Source clock for submodule 0 cannot be itself */
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if ((config->clockSource == kPWM_Submodule0Clock) && (subModule == kPWM_Module_0))
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{
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return kStatus_Fail;
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}
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/* Reload source select clock for submodule 0 cannot be master reload */
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if ((config->reloadSelect == kPWM_MasterReload) && (subModule == kPWM_Module_0))
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{
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return kStatus_Fail;
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}
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate the PWM submodule clock*/
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CLOCK_EnableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Clear the fault status flags */
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base->FSTS |= PWM_FSTS_FFLAG_MASK;
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reg = base->SM[subModule].CTRL2;
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/* Setup the submodule clock-source, control source of the INIT signal,
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* source of the force output signal, operation in debug & wait modes and reload source select
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*/
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reg &= ~(uint16_t)(PWM_CTRL2_CLK_SEL_MASK | PWM_CTRL2_FORCE_SEL_MASK | PWM_CTRL2_INIT_SEL_MASK |
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PWM_CTRL2_INDEP_MASK | PWM_CTRL2_WAITEN_MASK | PWM_CTRL2_DBGEN_MASK | PWM_CTRL2_RELOAD_SEL_MASK);
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reg |= (PWM_CTRL2_CLK_SEL(config->clockSource) | PWM_CTRL2_FORCE_SEL(config->forceTrigger) |
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PWM_CTRL2_INIT_SEL(config->initializationControl) | PWM_CTRL2_DBGEN(config->enableDebugMode) |
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PWM_CTRL2_WAITEN(config->enableWait) | PWM_CTRL2_RELOAD_SEL(config->reloadSelect));
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/* Setup PWM A & B to be independent or a complementary-pair */
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switch (config->pairOperation)
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{
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case kPWM_Independent:
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reg |= PWM_CTRL2_INDEP_MASK;
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break;
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case kPWM_ComplementaryPwmA:
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base->MCTRL &= ~((uint16_t)1U << (PWM_MCTRL_IPOL_SHIFT + (uint16_t)subModule));
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break;
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case kPWM_ComplementaryPwmB:
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base->MCTRL |= ((uint16_t)1U << (PWM_MCTRL_IPOL_SHIFT + (uint16_t)subModule));
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break;
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default:
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assert(false);
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break;
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}
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base->SM[subModule].CTRL2 = reg;
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reg = base->SM[subModule].CTRL;
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/* Setup the clock prescale, load mode and frequency */
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reg &= ~(uint16_t)(PWM_CTRL_PRSC_MASK | PWM_CTRL_LDFQ_MASK | PWM_CTRL_LDMOD_MASK);
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reg |= (PWM_CTRL_PRSC(config->prescale) | PWM_CTRL_LDFQ(config->reloadFrequency));
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/* Setup register reload logic */
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switch (config->reloadLogic)
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{
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case kPWM_ReloadImmediate:
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reg |= PWM_CTRL_LDMOD_MASK;
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break;
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case kPWM_ReloadPwmHalfCycle:
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reg |= PWM_CTRL_HALF_MASK;
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reg &= (uint16_t)(~PWM_CTRL_FULL_MASK);
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break;
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case kPWM_ReloadPwmFullCycle:
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reg &= (uint16_t)(~PWM_CTRL_HALF_MASK);
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reg |= PWM_CTRL_FULL_MASK;
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break;
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case kPWM_ReloadPwmHalfAndFullCycle:
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reg |= PWM_CTRL_HALF_MASK;
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reg |= PWM_CTRL_FULL_MASK;
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break;
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default:
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assert(false);
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break;
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}
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base->SM[subModule].CTRL = reg;
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/* Issue a Force trigger event when configured to trigger locally */
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if (config->forceTrigger == kPWM_Force_Local)
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{
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base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE(1U);
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}
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return kStatus_Success;
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}
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/*!
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* brief Gate the PWM submodule clock
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*
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* param base PWM peripheral base address
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* param subModule PWM submodule to deinitialize
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*/
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void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule)
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{
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/* Stop the submodule */
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base->MCTRL &= ~((uint16_t)1U << (PWM_MCTRL_RUN_SHIFT + (uint16_t)subModule));
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Gate the PWM submodule clock*/
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CLOCK_DisableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Fill in the PWM config struct with the default settings
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*
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* The default values are:
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* code
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* config->enableDebugMode = false;
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* config->enableWait = false;
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* config->reloadSelect = kPWM_LocalReload;
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* config->clockSource = kPWM_BusClock;
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* config->prescale = kPWM_Prescale_Divide_1;
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* config->initializationControl = kPWM_Initialize_LocalSync;
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* config->forceTrigger = kPWM_Force_Local;
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* config->reloadFrequency = kPWM_LoadEveryOportunity;
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* config->reloadLogic = kPWM_ReloadImmediate;
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* config->pairOperation = kPWM_Independent;
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* endcode
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* param config Pointer to user's PWM config structure.
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*/
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void PWM_GetDefaultConfig(pwm_config_t *config)
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{
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assert(config);
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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/* PWM is paused in debug mode */
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config->enableDebugMode = false;
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/* PWM is paused in wait mode */
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config->enableWait = false;
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/* PWM module uses the local reload signal to reload registers */
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config->reloadSelect = kPWM_LocalReload;
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/* Use the IP Bus clock as source clock for the PWM submodule */
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config->clockSource = kPWM_BusClock;
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/* Clock source prescale is set to divide by 1*/
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config->prescale = kPWM_Prescale_Divide_1;
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/* Local sync causes initialization */
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config->initializationControl = kPWM_Initialize_LocalSync;
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/* The local force signal, CTRL2[FORCE], from the submodule is used to force updates */
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config->forceTrigger = kPWM_Force_Local;
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/* PWM reload frequency, reload opportunity is PWM half cycle or full cycle.
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* This field is not used in Immediate reload mode
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*/
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config->reloadFrequency = kPWM_LoadEveryOportunity;
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/* Buffered-registers get loaded with new values as soon as LDOK bit is set */
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config->reloadLogic = kPWM_ReloadImmediate;
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/* PWM A & PWM B operate as 2 independent channels */
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config->pairOperation = kPWM_Independent;
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}
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/*!
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* brief Sets up the PWM signals for a PWM submodule.
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*
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* The function initializes the submodule according to the parameters passed in by the user. The function
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* also sets up the value compare registers to match the PWM signal requirements.
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* If the dead time insertion logic is enabled, the pulse period is reduced by the
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* dead time period specified by the user.
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*
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* param base PWM peripheral base address
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* param subModule PWM submodule to configure
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* param chnlParams Array of PWM channel parameters to configure the channel(s)
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* param numOfChnls Number of channels to configure, this should be the size of the array passed in.
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* Array size should not be more than 2 as each submodule has 2 pins to output PWM
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* param mode PWM operation mode, options available in enumeration ::pwm_mode_t
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* param pwmFreq_Hz PWM signal frequency in Hz
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* param srcClock_Hz PWM main counter clock in Hz.
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*
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* return Returns kStatusFail if there was error setting up the signal; kStatusSuccess otherwise
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*/
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status_t PWM_SetupPwm(PWM_Type *base,
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pwm_submodule_t subModule,
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const pwm_signal_param_t *chnlParams,
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uint8_t numOfChnls,
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pwm_mode_t mode,
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uint32_t pwmFreq_Hz,
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uint32_t srcClock_Hz)
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{
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assert(chnlParams);
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assert(pwmFreq_Hz);
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assert(numOfChnls);
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assert(srcClock_Hz);
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uint32_t pwmClock;
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uint16_t pulseCnt = 0, pwmHighPulse = 0;
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uint16_t modulo = 0;
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uint8_t i, polarityShift = 0, outputEnableShift = 0;
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if (numOfChnls > 2U)
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{
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/* Each submodule has 2 signals; PWM A & PWM B */
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return kStatus_Fail;
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}
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/* Divide the clock by the prescale value */
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pwmClock = (srcClock_Hz / (1UL << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT)));
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pulseCnt = (uint16_t)(pwmClock / pwmFreq_Hz);
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/* Setup each PWM channel */
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for (i = 0; i < numOfChnls; i++)
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{
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/* Calculate pulse width */
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pwmHighPulse = (pulseCnt * chnlParams->dutyCyclePercent) / 100U;
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/* Setup the different match registers to generate the PWM signal */
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switch (mode)
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{
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case kPWM_SignedCenterAligned:
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/* Setup the PWM period for a signed center aligned signal */
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if (i == 0U)
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{
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modulo = (pulseCnt >> 1U);
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/* Indicates the start of the PWM period */
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base->SM[subModule].INIT = PWM_GetComplementU16(modulo);
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/* Indicates the center value */
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base->SM[subModule].VAL0 = 0;
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/* Indicates the end of the PWM period */
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/* The change during the end to start of the PWM period requires a count time */
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base->SM[subModule].VAL1 = modulo - 1U;
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}
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/* Setup the PWM dutycycle */
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if (chnlParams->pwmChannel == kPWM_PwmA)
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{
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base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U);
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base->SM[subModule].VAL3 = (pwmHighPulse / 2U);
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}
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else
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{
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base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U);
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base->SM[subModule].VAL5 = (pwmHighPulse / 2U);
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}
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break;
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case kPWM_CenterAligned:
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/* Setup the PWM period for an unsigned center aligned signal */
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/* Indicates the start of the PWM period */
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if (i == 0U)
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{
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base->SM[subModule].INIT = 0;
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/* Indicates the center value */
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base->SM[subModule].VAL0 = (pulseCnt / 2U);
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/* Indicates the end of the PWM period */
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/* The change during the end to start of the PWM period requires a count time */
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base->SM[subModule].VAL1 = pulseCnt - 1U;
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}
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/* Setup the PWM dutycycle */
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if (chnlParams->pwmChannel == kPWM_PwmA)
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{
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base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U);
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base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U);
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}
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else
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{
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base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U);
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base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U);
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}
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break;
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case kPWM_SignedEdgeAligned:
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/* Setup the PWM period for a signed edge aligned signal */
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if (i == 0U)
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{
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modulo = (pulseCnt >> 1U);
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/* Indicates the start of the PWM period */
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base->SM[subModule].INIT = PWM_GetComplementU16(modulo);
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/* Indicates the center value */
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base->SM[subModule].VAL0 = 0;
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/* Indicates the end of the PWM period */
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/* The change during the end to start of the PWM period requires a count time */
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base->SM[subModule].VAL1 = modulo - 1U;
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}
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/* Setup the PWM dutycycle */
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if (chnlParams->pwmChannel == kPWM_PwmA)
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{
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base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo);
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base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse;
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}
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else
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{
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base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo);
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base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse;
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}
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break;
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case kPWM_EdgeAligned:
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/* Setup the PWM period for a unsigned edge aligned signal */
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/* Indicates the start of the PWM period */
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if (i == 0U)
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{
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base->SM[subModule].INIT = 0;
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/* Indicates the center value */
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base->SM[subModule].VAL0 = (pulseCnt / 2U);
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/* Indicates the end of the PWM period */
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/* The change during the end to start of the PWM period requires a count time */
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base->SM[subModule].VAL1 = pulseCnt - 1U;
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}
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/* Setup the PWM dutycycle */
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if (chnlParams->pwmChannel == kPWM_PwmA)
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{
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base->SM[subModule].VAL2 = 0;
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base->SM[subModule].VAL3 = pwmHighPulse;
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}
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else
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{
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base->SM[subModule].VAL4 = 0;
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base->SM[subModule].VAL5 = pwmHighPulse;
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}
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break;
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default:
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assert(false);
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break;
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}
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/* Setup register shift values based on the channel being configured.
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* Also setup the deadtime value
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*/
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if (chnlParams->pwmChannel == kPWM_PwmA)
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{
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polarityShift = PWM_OCTRL_POLA_SHIFT;
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outputEnableShift = PWM_OUTEN_PWMA_EN_SHIFT;
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base->SM[subModule].DTCNT0 = PWM_DTCNT0_DTCNT0(chnlParams->deadtimeValue);
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}
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else
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{
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polarityShift = PWM_OCTRL_POLB_SHIFT;
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outputEnableShift = PWM_OUTEN_PWMB_EN_SHIFT;
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base->SM[subModule].DTCNT1 = PWM_DTCNT1_DTCNT1(chnlParams->deadtimeValue);
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}
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/* Set PWM output fault status */
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switch (chnlParams->pwmChannel)
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{
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case kPWM_PwmA:
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base->SM[subModule].OCTRL &= ~((uint16_t)PWM_OCTRL_PWMAFS_MASK);
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base->SM[subModule].OCTRL |= (((uint16_t)(chnlParams->faultState) << (uint16_t)PWM_OCTRL_PWMAFS_SHIFT) &
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(uint16_t)PWM_OCTRL_PWMAFS_MASK);
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break;
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case kPWM_PwmB:
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base->SM[subModule].OCTRL &= ~((uint16_t)PWM_OCTRL_PWMBFS_MASK);
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base->SM[subModule].OCTRL |= (((uint16_t)(chnlParams->faultState) << (uint16_t)PWM_OCTRL_PWMBFS_SHIFT) &
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(uint16_t)PWM_OCTRL_PWMBFS_MASK);
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break;
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case kPWM_PwmX:
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base->SM[subModule].OCTRL &= ~((uint16_t)PWM_OCTRL_PWMXFS_MASK);
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base->SM[subModule].OCTRL |= (((uint16_t)(chnlParams->faultState) << (uint16_t)PWM_OCTRL_PWMXFS_SHIFT) &
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(uint16_t)PWM_OCTRL_PWMXFS_MASK);
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break;
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default:
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assert(false);
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break;
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}
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/* Setup signal active level */
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if ((bool)chnlParams->level == kPWM_HighTrue)
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{
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base->SM[subModule].OCTRL &= ~((uint16_t)1U << (uint16_t)polarityShift);
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}
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else
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{
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base->SM[subModule].OCTRL |= ((uint16_t)1U << (uint16_t)polarityShift);
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}
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/* Enable PWM output */
|
|
base->OUTEN |= ((uint16_t)1U << ((uint16_t)outputEnableShift + (uint16_t)subModule));
|
|
|
|
/* Get the next channel parameters */
|
|
chnlParams++;
|
|
}
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
/*!
|
|
* brief Updates the PWM signal's dutycycle.
|
|
*
|
|
* The function updates the PWM dutycyle to the new value that is passed in.
|
|
* If the dead time insertion logic is enabled then the pulse period is reduced by the
|
|
* dead time period specified by the user.
|
|
*
|
|
* param base PWM peripheral base address
|
|
* param subModule PWM submodule to configure
|
|
* param pwmSignal Signal (PWM A or PWM B) to update
|
|
* param currPwmMode The current PWM mode set during PWM setup
|
|
* param dutyCyclePercent New PWM pulse width, value should be between 0 to 100
|
|
* 0=inactive signal(0% duty cycle)...
|
|
* 100=active signal (100% duty cycle)
|
|
*/
|
|
void PWM_UpdatePwmDutycycle(PWM_Type *base,
|
|
pwm_submodule_t subModule,
|
|
pwm_channels_t pwmSignal,
|
|
pwm_mode_t currPwmMode,
|
|
uint8_t dutyCyclePercent)
|
|
{
|
|
assert(dutyCyclePercent <= 100U);
|
|
assert((uint16_t)pwmSignal < 2U);
|
|
uint16_t reloadValue = dutyCycleToReloadValue(dutyCyclePercent);
|
|
|
|
PWM_UpdatePwmDutycycleHighAccuracy(base, subModule, pwmSignal, currPwmMode, reloadValue);
|
|
}
|
|
|
|
/*!
|
|
* brief Updates the PWM signal's dutycycle with 16-bit accuracy.
|
|
*
|
|
* The function updates the PWM dutycyle to the new value that is passed in.
|
|
* If the dead time insertion logic is enabled then the pulse period is reduced by the
|
|
* dead time period specified by the user.
|
|
*
|
|
* param base PWM peripheral base address
|
|
* param subModule PWM submodule to configure
|
|
* param pwmSignal Signal (PWM A or PWM B) to update
|
|
* param currPwmMode The current PWM mode set during PWM setup
|
|
* param dutyCycle New PWM pulse width, value should be between 0 to 65535
|
|
* 0=inactive signal(0% duty cycle)...
|
|
* 65535=active signal (100% duty cycle)
|
|
*/
|
|
void PWM_UpdatePwmDutycycleHighAccuracy(
|
|
PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle)
|
|
{
|
|
assert((uint16_t)pwmSignal < 2U);
|
|
uint16_t pulseCnt = 0, pwmHighPulse = 0;
|
|
uint16_t modulo = 0;
|
|
|
|
switch (currPwmMode)
|
|
{
|
|
case kPWM_SignedCenterAligned:
|
|
modulo = base->SM[subModule].VAL1 + 1U;
|
|
pulseCnt = modulo * 2U;
|
|
/* Calculate pulse width */
|
|
pwmHighPulse = (pulseCnt * dutyCycle) / 65535U;
|
|
|
|
/* Setup the PWM dutycycle */
|
|
if (pwmSignal == kPWM_PwmA)
|
|
{
|
|
base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U);
|
|
base->SM[subModule].VAL3 = (pwmHighPulse / 2U);
|
|
}
|
|
else
|
|
{
|
|
base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U);
|
|
base->SM[subModule].VAL5 = (pwmHighPulse / 2U);
|
|
}
|
|
break;
|
|
case kPWM_CenterAligned:
|
|
pulseCnt = base->SM[subModule].VAL1 + 1U;
|
|
/* Calculate pulse width */
|
|
pwmHighPulse = (pulseCnt * dutyCycle) / 65535U;
|
|
|
|
/* Setup the PWM dutycycle */
|
|
if (pwmSignal == kPWM_PwmA)
|
|
{
|
|
base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U);
|
|
base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U);
|
|
}
|
|
else
|
|
{
|
|
base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U);
|
|
base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U);
|
|
}
|
|
break;
|
|
case kPWM_SignedEdgeAligned:
|
|
modulo = base->SM[subModule].VAL1 + 1U;
|
|
pulseCnt = modulo * 2U;
|
|
/* Calculate pulse width */
|
|
pwmHighPulse = (pulseCnt * dutyCycle) / 65535U;
|
|
|
|
/* Setup the PWM dutycycle */
|
|
if (pwmSignal == kPWM_PwmA)
|
|
{
|
|
base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo);
|
|
base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse;
|
|
}
|
|
else
|
|
{
|
|
base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo);
|
|
base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse;
|
|
}
|
|
break;
|
|
case kPWM_EdgeAligned:
|
|
pulseCnt = base->SM[subModule].VAL1 + 1U;
|
|
/* Calculate pulse width */
|
|
pwmHighPulse = (pulseCnt * dutyCycle) / 65535U;
|
|
|
|
/* Setup the PWM dutycycle */
|
|
if (pwmSignal == kPWM_PwmA)
|
|
{
|
|
base->SM[subModule].VAL2 = 0;
|
|
base->SM[subModule].VAL3 = pwmHighPulse;
|
|
}
|
|
else
|
|
{
|
|
base->SM[subModule].VAL4 = 0;
|
|
base->SM[subModule].VAL5 = pwmHighPulse;
|
|
}
|
|
break;
|
|
default:
|
|
assert(false);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief Sets up the PWM input capture
|
|
*
|
|
* Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function
|
|
* sets up the capture parameters for each pin and enables the pin for input capture operation.
|
|
*
|
|
* param base PWM peripheral base address
|
|
* param subModule PWM submodule to configure
|
|
* param pwmChannel Channel in the submodule to setup
|
|
* param inputCaptureParams Parameters passed in to set up the input pin
|
|
*/
|
|
void PWM_SetupInputCapture(PWM_Type *base,
|
|
pwm_submodule_t subModule,
|
|
pwm_channels_t pwmChannel,
|
|
const pwm_input_capture_param_t *inputCaptureParams)
|
|
{
|
|
uint16_t reg = 0;
|
|
switch (pwmChannel)
|
|
{
|
|
case kPWM_PwmA:
|
|
/* Setup the capture paramters for PWM A pin */
|
|
reg = (PWM_CAPTCTRLA_INP_SELA(inputCaptureParams->captureInputSel) |
|
|
PWM_CAPTCTRLA_EDGA0(inputCaptureParams->edge0) | PWM_CAPTCTRLA_EDGA1(inputCaptureParams->edge1) |
|
|
PWM_CAPTCTRLA_ONESHOTA(inputCaptureParams->enableOneShotCapture) |
|
|
PWM_CAPTCTRLA_CFAWM(inputCaptureParams->fifoWatermark));
|
|
/* Enable the edge counter if using the output edge counter */
|
|
if (inputCaptureParams->captureInputSel)
|
|
{
|
|
reg |= PWM_CAPTCTRLA_EDGCNTA_EN_MASK;
|
|
}
|
|
/* Enable input capture operation */
|
|
reg |= PWM_CAPTCTRLA_ARMA_MASK;
|
|
|
|
base->SM[subModule].CAPTCTRLA = reg;
|
|
|
|
/* Setup the compare value when using the edge counter as source */
|
|
base->SM[subModule].CAPTCOMPA = PWM_CAPTCOMPA_EDGCMPA(inputCaptureParams->edgeCompareValue);
|
|
/* Setup PWM A pin for input capture */
|
|
base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMA_EN_SHIFT + (uint16_t)subModule));
|
|
break;
|
|
case kPWM_PwmB:
|
|
/* Setup the capture paramters for PWM B pin */
|
|
reg = (PWM_CAPTCTRLB_INP_SELB(inputCaptureParams->captureInputSel) |
|
|
PWM_CAPTCTRLB_EDGB0(inputCaptureParams->edge0) | PWM_CAPTCTRLB_EDGB1(inputCaptureParams->edge1) |
|
|
PWM_CAPTCTRLB_ONESHOTB(inputCaptureParams->enableOneShotCapture) |
|
|
PWM_CAPTCTRLB_CFBWM(inputCaptureParams->fifoWatermark));
|
|
/* Enable the edge counter if using the output edge counter */
|
|
if (inputCaptureParams->captureInputSel)
|
|
{
|
|
reg |= PWM_CAPTCTRLB_EDGCNTB_EN_MASK;
|
|
}
|
|
/* Enable input capture operation */
|
|
reg |= PWM_CAPTCTRLB_ARMB_MASK;
|
|
|
|
base->SM[subModule].CAPTCTRLB = reg;
|
|
|
|
/* Setup the compare value when using the edge counter as source */
|
|
base->SM[subModule].CAPTCOMPB = PWM_CAPTCOMPB_EDGCMPB(inputCaptureParams->edgeCompareValue);
|
|
/* Setup PWM B pin for input capture */
|
|
base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMB_EN_SHIFT + (uint16_t)subModule));
|
|
break;
|
|
case kPWM_PwmX:
|
|
reg = (PWM_CAPTCTRLX_INP_SELX(inputCaptureParams->captureInputSel) |
|
|
PWM_CAPTCTRLX_EDGX0(inputCaptureParams->edge0) | PWM_CAPTCTRLX_EDGX1(inputCaptureParams->edge1) |
|
|
PWM_CAPTCTRLX_ONESHOTX(inputCaptureParams->enableOneShotCapture) |
|
|
PWM_CAPTCTRLX_CFXWM(inputCaptureParams->fifoWatermark));
|
|
/* Enable the edge counter if using the output edge counter */
|
|
if (inputCaptureParams->captureInputSel)
|
|
{
|
|
reg |= PWM_CAPTCTRLX_EDGCNTX_EN_MASK;
|
|
}
|
|
/* Enable input capture operation */
|
|
reg |= PWM_CAPTCTRLX_ARMX_MASK;
|
|
|
|
base->SM[subModule].CAPTCTRLX = reg;
|
|
|
|
/* Setup the compare value when using the edge counter as source */
|
|
base->SM[subModule].CAPTCOMPX = PWM_CAPTCOMPX_EDGCMPX(inputCaptureParams->edgeCompareValue);
|
|
/* Setup PWM X pin for input capture */
|
|
base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMX_EN_SHIFT + (uint16_t)subModule));
|
|
break;
|
|
default:
|
|
assert(false);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* @brief Sets up the PWM fault input filter.
|
|
*
|
|
* @param base PWM peripheral base address
|
|
* @param faultInputFilterParams Parameters passed in to set up the fault input filter.
|
|
*/
|
|
void PWM_SetupFaultInputFilter(PWM_Type *base, const pwm_fault_input_filter_param_t *faultInputFilterParams)
|
|
{
|
|
assert(NULL != faultInputFilterParams);
|
|
|
|
/* When changing values for fault period from a non-zero value, first write a value of 0 to clear the filter. */
|
|
if (0U != (base->FFILT & PWM_FFILT_FILT_PER_MASK))
|
|
{
|
|
base->FFILT &= ~(uint16_t)(PWM_FFILT_FILT_PER_MASK);
|
|
}
|
|
|
|
base->FFILT = (uint16_t)(PWM_FFILT_FILT_PER(faultInputFilterParams->faultFilterPeriod) |
|
|
PWM_FFILT_FILT_CNT(faultInputFilterParams->faultFilterCount) |
|
|
PWM_FFILT_GSTR(faultInputFilterParams->faultGlitchStretch ? 1U : 0U));
|
|
}
|
|
|
|
/*!
|
|
* brief Sets up the PWM fault protection.
|
|
*
|
|
* PWM has 4 fault inputs.
|
|
*
|
|
* param base PWM peripheral base address
|
|
* param faultNum PWM fault to configure.
|
|
* param faultParams Pointer to the PWM fault config structure
|
|
*/
|
|
void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams)
|
|
{
|
|
assert(faultParams);
|
|
uint16_t reg;
|
|
|
|
reg = base->FCTRL;
|
|
/* Set the faults level-settting */
|
|
if (faultParams->faultLevel)
|
|
{
|
|
reg |= ((uint16_t)1U << (PWM_FCTRL_FLVL_SHIFT + (uint16_t)faultNum));
|
|
}
|
|
else
|
|
{
|
|
reg &= ~((uint16_t)1U << (PWM_FCTRL_FLVL_SHIFT + (uint16_t)faultNum));
|
|
}
|
|
/* Set the fault clearing mode */
|
|
if ((uint16_t)faultParams->faultClearingMode != 0U)
|
|
{
|
|
/* Use manual fault clearing */
|
|
reg &= ~((uint16_t)1U << (PWM_FCTRL_FAUTO_SHIFT + (uint16_t)faultNum));
|
|
if (faultParams->faultClearingMode == kPWM_ManualSafety)
|
|
{
|
|
/* Use manual fault clearing with safety mode enabled */
|
|
reg |= ((uint16_t)1U << (PWM_FCTRL_FSAFE_SHIFT + (uint16_t)faultNum));
|
|
}
|
|
else
|
|
{
|
|
/* Use manual fault clearing with safety mode disabled */
|
|
reg &= ~((uint16_t)1U << (PWM_FCTRL_FSAFE_SHIFT + (uint16_t)faultNum));
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Use automatic fault clearing */
|
|
reg |= ((uint16_t)1U << (PWM_FCTRL_FAUTO_SHIFT + (uint16_t)faultNum));
|
|
}
|
|
base->FCTRL = reg;
|
|
|
|
/* Set the combinational path option */
|
|
if (faultParams->enableCombinationalPath)
|
|
{
|
|
/* Combinational path from the fault input to the PWM output is available */
|
|
base->FCTRL2 &= ~((uint16_t)1U << (uint16_t)faultNum);
|
|
}
|
|
else
|
|
{
|
|
/* No combinational path available, only fault filter & latch signal can disable PWM output */
|
|
base->FCTRL2 |= ((uint16_t)1U << (uint16_t)faultNum);
|
|
}
|
|
|
|
/* Initially clear both recovery modes */
|
|
reg = base->FSTS;
|
|
reg &= ~(((uint16_t)1U << (PWM_FSTS_FFULL_SHIFT + (uint16_t)faultNum)) |
|
|
((uint16_t)1U << (PWM_FSTS_FHALF_SHIFT + (uint16_t)faultNum)));
|
|
/* Setup fault recovery */
|
|
switch (faultParams->recoverMode)
|
|
{
|
|
case kPWM_NoRecovery:
|
|
break;
|
|
case kPWM_RecoverHalfCycle:
|
|
reg |= ((uint16_t)1U << (PWM_FSTS_FHALF_SHIFT + (uint16_t)faultNum));
|
|
break;
|
|
case kPWM_RecoverFullCycle:
|
|
reg |= ((uint16_t)1U << (PWM_FSTS_FFULL_SHIFT + (uint16_t)faultNum));
|
|
break;
|
|
case kPWM_RecoverHalfAndFullCycle:
|
|
reg |= ((uint16_t)1U << (PWM_FSTS_FHALF_SHIFT + (uint16_t)faultNum));
|
|
reg |= ((uint16_t)1U << (PWM_FSTS_FFULL_SHIFT + (uint16_t)faultNum));
|
|
break;
|
|
default:
|
|
assert(false);
|
|
break;
|
|
}
|
|
base->FSTS = reg;
|
|
}
|
|
|
|
/*!
|
|
* brief Fill in the PWM fault config struct with the default settings
|
|
*
|
|
* The default values are:
|
|
* code
|
|
* config->faultClearingMode = kPWM_Automatic;
|
|
* config->faultLevel = false;
|
|
* config->enableCombinationalPath = true;
|
|
* config->recoverMode = kPWM_NoRecovery;
|
|
* endcode
|
|
* param config Pointer to user's PWM fault config structure.
|
|
*/
|
|
void PWM_FaultDefaultConfig(pwm_fault_param_t *config)
|
|
{
|
|
assert(config);
|
|
|
|
/* Initializes the configure structure to zero. */
|
|
(void)memset(config, 0, sizeof(*config));
|
|
|
|
/* PWM uses automatic fault clear mode */
|
|
config->faultClearingMode = kPWM_Automatic;
|
|
/* PWM fault level is set to logic 0 */
|
|
config->faultLevel = false;
|
|
/* Combinational Path from fault input is enabled */
|
|
config->enableCombinationalPath = true;
|
|
/* PWM output will stay inactive when recovering from a fault */
|
|
config->recoverMode = kPWM_NoRecovery;
|
|
}
|
|
|
|
/*!
|
|
* brief Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted.
|
|
*
|
|
* The user specifies which channel to configure by supplying the submodule number and whether
|
|
* to modify PWM A or PWM B within that submodule.
|
|
*
|
|
* param base PWM peripheral base address
|
|
* param subModule PWM submodule to configure
|
|
* param pwmChannel Channel to configure
|
|
* param mode Signal to output when a FORCE_OUT is triggered
|
|
*/
|
|
void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_force_signal_t mode)
|
|
|
|
{
|
|
uint16_t shift;
|
|
uint16_t reg;
|
|
|
|
/* DTSRCSEL register has 4 bits per submodule; 2 bits for PWM A and 2 bits for PWM B */
|
|
shift = ((uint16_t)subModule * 4U) + ((uint16_t)pwmChannel * 2U);
|
|
|
|
/* Setup the signal to be passed upon occurrence of a FORCE_OUT signal */
|
|
reg = base->DTSRCSEL;
|
|
reg &= ~((uint16_t)0x3U << shift);
|
|
reg |= (uint16_t)((uint16_t)mode << shift);
|
|
base->DTSRCSEL = reg;
|
|
}
|
|
|
|
/*!
|
|
* brief Enables the selected PWM interrupts
|
|
*
|
|
* param base PWM peripheral base address
|
|
* param subModule PWM submodule to configure
|
|
* param mask The interrupts to enable. This is a logical OR of members of the
|
|
* enumeration ::pwm_interrupt_enable_t
|
|
*/
|
|
void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)
|
|
{
|
|
/* Upper 16 bits are for related to the submodule */
|
|
base->SM[subModule].INTEN |= ((uint16_t)mask & 0xFFFFU);
|
|
/* Fault related interrupts */
|
|
base->FCTRL |= ((uint16_t)(mask >> 16U) & PWM_FCTRL_FIE_MASK);
|
|
}
|
|
|
|
/*!
|
|
* brief Disables the selected PWM interrupts
|
|
*
|
|
* param base PWM peripheral base address
|
|
* param subModule PWM submodule to configure
|
|
* param mask The interrupts to enable. This is a logical OR of members of the
|
|
* enumeration ::pwm_interrupt_enable_t
|
|
*/
|
|
void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)
|
|
{
|
|
base->SM[subModule].INTEN &= ~((uint16_t)mask & 0xFFFFU);
|
|
base->FCTRL &= ~((uint16_t)(mask >> 16U) & PWM_FCTRL_FIE_MASK);
|
|
}
|
|
|
|
/*!
|
|
* brief Gets the enabled PWM interrupts
|
|
*
|
|
* param base PWM peripheral base address
|
|
* param subModule PWM submodule to configure
|
|
*
|
|
* return The enabled interrupts. This is the logical OR of members of the
|
|
* enumeration ::pwm_interrupt_enable_t
|
|
*/
|
|
uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule)
|
|
{
|
|
uint32_t enabledInterrupts;
|
|
|
|
enabledInterrupts = base->SM[subModule].INTEN;
|
|
enabledInterrupts |= (((uint32_t)base->FCTRL & PWM_FCTRL_FIE_MASK) << 16UL);
|
|
return enabledInterrupts;
|
|
}
|
|
|
|
/*!
|
|
* brief Gets the PWM status flags
|
|
*
|
|
* param base PWM peripheral base address
|
|
* param subModule PWM submodule to configure
|
|
*
|
|
* return The status flags. This is the logical OR of members of the
|
|
* enumeration ::pwm_status_flags_t
|
|
*/
|
|
uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule)
|
|
{
|
|
uint32_t statusFlags;
|
|
|
|
statusFlags = base->SM[subModule].STS;
|
|
statusFlags |= (((uint32_t)base->FSTS & PWM_FSTS_FFLAG_MASK) << 16UL);
|
|
|
|
return statusFlags;
|
|
}
|
|
|
|
/*!
|
|
* brief Clears the PWM status flags
|
|
*
|
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* param base PWM peripheral base address
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* param subModule PWM submodule to configure
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* param mask The status flags to clear. This is a logical OR of members of the
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* enumeration ::pwm_status_flags_t
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*/
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void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)
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{
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uint16_t reg;
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base->SM[subModule].STS = ((uint16_t)mask & 0xFFFFU);
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reg = base->FSTS;
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/* Clear the fault flags and set only the ones we wish to clear as the fault flags are cleared
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* by writing a login one
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*/
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reg &= ~(uint16_t)(PWM_FSTS_FFLAG_MASK);
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reg |= (uint16_t)((mask >> 16U) & PWM_FSTS_FFLAG_MASK);
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base->FSTS = reg;
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}
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