234 lines
7.1 KiB
C
234 lines
7.1 KiB
C
/*
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* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2021 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_common.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.common_arm"
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#endif
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#ifndef __GIC_PRIO_BITS
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#if defined(ENABLE_RAM_VECTOR_TABLE)
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uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
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{
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#ifdef __VECTOR_TABLE
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#undef __VECTOR_TABLE
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#endif
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/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
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extern uint32_t Image$$VECTOR_ROM$$Base[];
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extern uint32_t Image$$VECTOR_RAM$$Base[];
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extern uint32_t Image$$RW_m_data$$Base[];
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#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
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#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
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#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
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#elif defined(__ICCARM__)
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extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
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extern uint32_t __VECTOR_TABLE[];
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extern uint32_t __VECTOR_RAM[];
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#elif defined(__GNUC__)
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extern uint32_t __VECTOR_TABLE[];
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extern uint32_t __VECTOR_RAM[];
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extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
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uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
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#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
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uint32_t n;
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uint32_t ret;
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uint32_t irqMaskValue;
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irqMaskValue = DisableGlobalIRQ();
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if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
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{
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/* Copy the vector table from ROM to RAM */
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for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
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{
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__VECTOR_RAM[n] = __VECTOR_TABLE[n];
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}
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/* Point the VTOR to the position of vector table */
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SCB->VTOR = (uint32_t)__VECTOR_RAM;
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}
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ret = __VECTOR_RAM[(int32_t)irq + 16];
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/* make sure the __VECTOR_RAM is noncachable */
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__VECTOR_RAM[(int32_t)irq + 16] = irqHandler;
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EnableGlobalIRQ(irqMaskValue);
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return ret;
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}
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#endif /* ENABLE_RAM_VECTOR_TABLE. */
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#endif /* __GIC_PRIO_BITS. */
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#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
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/*
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* When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
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* powerlib should be used instead of these functions.
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*/
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#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
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/*
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* When the SYSCON STARTER registers are discontinuous, these functions are
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* implemented in fsl_power.c.
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*/
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#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
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void EnableDeepSleepIRQ(IRQn_Type interrupt)
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{
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uint32_t intNumber = (uint32_t)interrupt;
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uint32_t index = 0;
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while (intNumber >= 32u)
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{
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index++;
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intNumber -= 32u;
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}
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SYSCON->STARTERSET[index] = 1UL << intNumber;
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(void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */
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}
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void DisableDeepSleepIRQ(IRQn_Type interrupt)
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{
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uint32_t intNumber = (uint32_t)interrupt;
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(void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */
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uint32_t index = 0;
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while (intNumber >= 32u)
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{
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index++;
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intNumber -= 32u;
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}
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SYSCON->STARTERCLR[index] = 1UL << intNumber;
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}
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#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
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#endif /* FSL_FEATURE_POWERLIB_EXTEND */
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#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
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#if defined(SDK_DELAY_USE_DWT) && defined(DWT)
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/* Use WDT. */
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static void enableCpuCycleCounter(void)
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{
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/* Make sure the DWT trace fucntion is enabled. */
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if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
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{
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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}
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/* CYCCNT not supported on this device. */
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assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk));
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/* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */
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if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL))
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{
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DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
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}
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}
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static uint32_t getCpuCycleCount(void)
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{
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return DWT->CYCCNT;
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}
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#else /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
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/* Use software loop. */
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#if defined(__CC_ARM) /* This macro is arm v5 specific */
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/* clang-format off */
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__ASM static void DelayLoop(uint32_t count)
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{
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loop
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SUBS R0, R0, #1
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CMP R0, #0
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BNE loop
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BX LR
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}
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/* clang-format on */
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#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)
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/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,
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* use SUB and CMP here for compatibility */
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static void DelayLoop(uint32_t count)
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{
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__ASM volatile(" MOV R0, %0" : : "r"(count));
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__ASM volatile(
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"loop: \n"
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#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
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" SUB R0, R0, #1 \n"
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#else
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" SUBS R0, R0, #1 \n"
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#endif
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" CMP R0, #0 \n"
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" BNE loop \n"
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:
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:
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: "r0");
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}
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#endif /* defined(__CC_ARM) */
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#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
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/*!
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* @brief Delay at least for some time.
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* Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have
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* effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and
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* coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports
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* up to 4294967 in current code. If long time delay is needed, please implement a new delay function.
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*
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* @param delayTime_us Delay time in unit of microsecond.
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* @param coreClock_Hz Core clock frequency with Hz.
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*/
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void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
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{
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uint64_t count;
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if (delayTime_us > 0U)
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{
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count = USEC_TO_COUNT(delayTime_us, coreClock_Hz);
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assert(count <= UINT32_MAX);
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#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */
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enableCpuCycleCounter();
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/* Calculate the count ticks. */
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count += getCpuCycleCount();
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if (count > UINT32_MAX)
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{
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count -= UINT32_MAX;
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/* Wait for cyccnt overflow. */
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while (count < getCpuCycleCount())
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{
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}
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}
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/* Wait for cyccnt reach count value. */
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while (count > getCpuCycleCount())
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{
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}
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#else
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/* Divide value may be different in various environment to ensure delay is precise.
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* Every loop count includes three instructions, due to Cortex-M7 sometimes executes
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* two instructions in one period, through test here set divide 1.5. Other M cores use
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* divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does
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* not matter because other instructions outside while loop is enough to fill the time.
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*/
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#if (__CORTEX_M == 7)
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count = count / 3U * 2U;
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#else
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count = count / 4U;
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#endif
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DelayLoop((uint32_t)count);
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#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
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}
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}
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