731 lines
25 KiB
C
731 lines
25 KiB
C
/*
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* Copyright (c) 2014, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*
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* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
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*
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* This file was generated automatically and any changes may be lost.
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*/
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#ifndef __HW_RCM_REGISTERS_H__
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#define __HW_RCM_REGISTERS_H__
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#include "regs.h"
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/*
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* MK64F12 RCM
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*
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* Reset Control Module
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*
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* Registers defined in this header file:
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* - HW_RCM_SRS0 - System Reset Status Register 0
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* - HW_RCM_SRS1 - System Reset Status Register 1
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* - HW_RCM_RPFC - Reset Pin Filter Control register
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* - HW_RCM_RPFW - Reset Pin Filter Width register
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* - HW_RCM_MR - Mode Register
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*
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* - hw_rcm_t - Struct containing all module registers.
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*/
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//! @name Module base addresses
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//@{
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#ifndef REGS_RCM_BASE
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#define HW_RCM_INSTANCE_COUNT (1U) //!< Number of instances of the RCM module.
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#define REGS_RCM_BASE (0x4007F000U) //!< Base address for RCM.
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_RCM_SRS0 - System Reset Status Register 0
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_RCM_SRS0 - System Reset Status Register 0 (RO)
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*
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* Reset value: 0x82U
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*
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* This register includes read-only status flags to indicate the source of the
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* most recent reset. The reset state of these bits depends on what caused the MCU
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* to reset. The reset value of this register depends on the reset source: POR
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* (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
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* pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
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* reset - a bit is set if its corresponding reset source caused the reset
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*/
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typedef union _hw_rcm_srs0
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{
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uint8_t U;
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struct _hw_rcm_srs0_bitfields
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{
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uint8_t WAKEUP : 1; //!< [0] Low Leakage Wakeup Reset
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uint8_t LVD : 1; //!< [1] Low-Voltage Detect Reset
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uint8_t LOC : 1; //!< [2] Loss-of-Clock Reset
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uint8_t LOL : 1; //!< [3] Loss-of-Lock Reset
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uint8_t RESERVED0 : 1; //!< [4]
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uint8_t WDOGb : 1; //!< [5] Watchdog
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uint8_t PIN : 1; //!< [6] External Reset Pin
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uint8_t POR : 1; //!< [7] Power-On Reset
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} B;
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} hw_rcm_srs0_t;
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#endif
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/*!
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* @name Constants and macros for entire RCM_SRS0 register
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*/
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//@{
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#define HW_RCM_SRS0_ADDR (REGS_RCM_BASE + 0x0U)
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#ifndef __LANGUAGE_ASM__
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#define HW_RCM_SRS0 (*(__I hw_rcm_srs0_t *) HW_RCM_SRS0_ADDR)
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#define HW_RCM_SRS0_RD() (HW_RCM_SRS0.U)
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#endif
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//@}
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/*
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* Constants & macros for individual RCM_SRS0 bitfields
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*/
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/*!
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* @name Register RCM_SRS0, field WAKEUP[0] (RO)
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*
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* Indicates a reset has been caused by an enabled LLWU module wakeup source
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* while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
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* wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
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* mode causes a reset. This bit is cleared by any reset except WAKEUP.
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*
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* Values:
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* - 0 - Reset not caused by LLWU module wakeup source
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* - 1 - Reset caused by LLWU module wakeup source
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*/
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//@{
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#define BP_RCM_SRS0_WAKEUP (0U) //!< Bit position for RCM_SRS0_WAKEUP.
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#define BM_RCM_SRS0_WAKEUP (0x01U) //!< Bit mask for RCM_SRS0_WAKEUP.
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#define BS_RCM_SRS0_WAKEUP (1U) //!< Bit field size in bits for RCM_SRS0_WAKEUP.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RCM_SRS0_WAKEUP field.
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#define BR_RCM_SRS0_WAKEUP (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_WAKEUP))
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#endif
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//@}
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/*!
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* @name Register RCM_SRS0, field LVD[1] (RO)
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*
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* If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
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* an LVD reset occurs. This field is also set by POR.
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*
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* Values:
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* - 0 - Reset not caused by LVD trip or POR
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* - 1 - Reset caused by LVD trip or POR
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*/
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//@{
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#define BP_RCM_SRS0_LVD (1U) //!< Bit position for RCM_SRS0_LVD.
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#define BM_RCM_SRS0_LVD (0x02U) //!< Bit mask for RCM_SRS0_LVD.
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#define BS_RCM_SRS0_LVD (1U) //!< Bit field size in bits for RCM_SRS0_LVD.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RCM_SRS0_LVD field.
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#define BR_RCM_SRS0_LVD (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LVD))
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#endif
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//@}
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/*!
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* @name Register RCM_SRS0, field LOC[2] (RO)
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*
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* Indicates a reset has been caused by a loss of external clock. The MCG clock
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* monitor must be enabled for a loss of clock to be detected. Refer to the
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* detailed MCG description for information on enabling the clock monitor.
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*
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* Values:
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* - 0 - Reset not caused by a loss of external clock.
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* - 1 - Reset caused by a loss of external clock.
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*/
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//@{
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#define BP_RCM_SRS0_LOC (2U) //!< Bit position for RCM_SRS0_LOC.
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#define BM_RCM_SRS0_LOC (0x04U) //!< Bit mask for RCM_SRS0_LOC.
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#define BS_RCM_SRS0_LOC (1U) //!< Bit field size in bits for RCM_SRS0_LOC.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RCM_SRS0_LOC field.
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#define BR_RCM_SRS0_LOC (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LOC))
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#endif
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//@}
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/*!
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* @name Register RCM_SRS0, field LOL[3] (RO)
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*
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* Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
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* MCG description for information on the loss-of-clock event.
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*
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* Values:
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* - 0 - Reset not caused by a loss of lock in the PLL
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* - 1 - Reset caused by a loss of lock in the PLL
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*/
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//@{
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#define BP_RCM_SRS0_LOL (3U) //!< Bit position for RCM_SRS0_LOL.
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#define BM_RCM_SRS0_LOL (0x08U) //!< Bit mask for RCM_SRS0_LOL.
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#define BS_RCM_SRS0_LOL (1U) //!< Bit field size in bits for RCM_SRS0_LOL.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RCM_SRS0_LOL field.
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#define BR_RCM_SRS0_LOL (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LOL))
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#endif
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//@}
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/*!
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* @name Register RCM_SRS0, field WDOG[5] (RO)
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*
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* Indicates a reset has been caused by the watchdog timer Computer Operating
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* Properly (COP) timing out. This reset source can be blocked by disabling the COP
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* watchdog: write 00 to SIM_COPCTRL[COPT].
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*
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* Values:
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* - 0 - Reset not caused by watchdog timeout
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* - 1 - Reset caused by watchdog timeout
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*/
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//@{
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#define BP_RCM_SRS0_WDOG (5U) //!< Bit position for RCM_SRS0_WDOG.
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#define BM_RCM_SRS0_WDOG (0x20U) //!< Bit mask for RCM_SRS0_WDOG.
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#define BS_RCM_SRS0_WDOG (1U) //!< Bit field size in bits for RCM_SRS0_WDOG.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RCM_SRS0_WDOG field.
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#define BR_RCM_SRS0_WDOG (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_WDOG))
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#endif
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//@}
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/*!
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* @name Register RCM_SRS0, field PIN[6] (RO)
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*
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* Indicates a reset has been caused by an active-low level on the external
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* RESET pin.
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*
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* Values:
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* - 0 - Reset not caused by external reset pin
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* - 1 - Reset caused by external reset pin
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*/
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//@{
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#define BP_RCM_SRS0_PIN (6U) //!< Bit position for RCM_SRS0_PIN.
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#define BM_RCM_SRS0_PIN (0x40U) //!< Bit mask for RCM_SRS0_PIN.
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#define BS_RCM_SRS0_PIN (1U) //!< Bit field size in bits for RCM_SRS0_PIN.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RCM_SRS0_PIN field.
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#define BR_RCM_SRS0_PIN (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_PIN))
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#endif
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//@}
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/*!
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* @name Register RCM_SRS0, field POR[7] (RO)
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*
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* Indicates a reset has been caused by the power-on detection logic. Because
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* the internal supply voltage was ramping up at the time, the low-voltage reset
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* (LVD) status bit is also set to indicate that the reset occurred while the
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* internal supply was below the LVD threshold.
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*
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* Values:
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* - 0 - Reset not caused by POR
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* - 1 - Reset caused by POR
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*/
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//@{
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#define BP_RCM_SRS0_POR (7U) //!< Bit position for RCM_SRS0_POR.
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#define BM_RCM_SRS0_POR (0x80U) //!< Bit mask for RCM_SRS0_POR.
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#define BS_RCM_SRS0_POR (1U) //!< Bit field size in bits for RCM_SRS0_POR.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RCM_SRS0_POR field.
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#define BR_RCM_SRS0_POR (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_POR))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_RCM_SRS1 - System Reset Status Register 1
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_RCM_SRS1 - System Reset Status Register 1 (RO)
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*
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* Reset value: 0x00U
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*
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* This register includes read-only status flags to indicate the source of the
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* most recent reset. The reset state of these bits depends on what caused the MCU
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* to reset. The reset value of this register depends on the reset source: POR
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* (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
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* reset - a bit is set if its corresponding reset source caused the reset
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*/
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typedef union _hw_rcm_srs1
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{
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uint8_t U;
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struct _hw_rcm_srs1_bitfields
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{
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uint8_t JTAG : 1; //!< [0] JTAG Generated Reset
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uint8_t LOCKUP : 1; //!< [1] Core Lockup
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uint8_t SW : 1; //!< [2] Software
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uint8_t MDM_AP : 1; //!< [3] MDM-AP System Reset Request
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uint8_t EZPT : 1; //!< [4] EzPort Reset
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uint8_t SACKERR : 1; //!< [5] Stop Mode Acknowledge Error Reset
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uint8_t RESERVED0 : 2; //!< [7:6]
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} B;
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} hw_rcm_srs1_t;
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#endif
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/*!
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* @name Constants and macros for entire RCM_SRS1 register
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*/
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//@{
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#define HW_RCM_SRS1_ADDR (REGS_RCM_BASE + 0x1U)
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#ifndef __LANGUAGE_ASM__
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#define HW_RCM_SRS1 (*(__I hw_rcm_srs1_t *) HW_RCM_SRS1_ADDR)
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#define HW_RCM_SRS1_RD() (HW_RCM_SRS1.U)
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#endif
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//@}
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/*
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* Constants & macros for individual RCM_SRS1 bitfields
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*/
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/*!
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* @name Register RCM_SRS1, field JTAG[0] (RO)
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*
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* Indicates a reset has been caused by JTAG selection of certain IR codes:
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* EZPORT, EXTEST, HIGHZ, and CLAMP.
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*
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* Values:
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* - 0 - Reset not caused by JTAG
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* - 1 - Reset caused by JTAG
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*/
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//@{
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#define BP_RCM_SRS1_JTAG (0U) //!< Bit position for RCM_SRS1_JTAG.
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#define BM_RCM_SRS1_JTAG (0x01U) //!< Bit mask for RCM_SRS1_JTAG.
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#define BS_RCM_SRS1_JTAG (1U) //!< Bit field size in bits for RCM_SRS1_JTAG.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RCM_SRS1_JTAG field.
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#define BR_RCM_SRS1_JTAG (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_JTAG))
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#endif
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//@}
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/*!
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* @name Register RCM_SRS1, field LOCKUP[1] (RO)
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*
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* Indicates a reset has been caused by the ARM core indication of a LOCKUP
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* event.
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*
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* Values:
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* - 0 - Reset not caused by core LOCKUP event
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* - 1 - Reset caused by core LOCKUP event
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*/
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//@{
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#define BP_RCM_SRS1_LOCKUP (1U) //!< Bit position for RCM_SRS1_LOCKUP.
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#define BM_RCM_SRS1_LOCKUP (0x02U) //!< Bit mask for RCM_SRS1_LOCKUP.
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#define BS_RCM_SRS1_LOCKUP (1U) //!< Bit field size in bits for RCM_SRS1_LOCKUP.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RCM_SRS1_LOCKUP field.
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#define BR_RCM_SRS1_LOCKUP (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_LOCKUP))
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#endif
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//@}
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/*!
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* @name Register RCM_SRS1, field SW[2] (RO)
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*
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* Indicates a reset has been caused by software setting of SYSRESETREQ bit in
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* Application Interrupt and Reset Control Register in the ARM core.
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*
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* Values:
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* - 0 - Reset not caused by software setting of SYSRESETREQ bit
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* - 1 - Reset caused by software setting of SYSRESETREQ bit
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*/
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//@{
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#define BP_RCM_SRS1_SW (2U) //!< Bit position for RCM_SRS1_SW.
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#define BM_RCM_SRS1_SW (0x04U) //!< Bit mask for RCM_SRS1_SW.
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#define BS_RCM_SRS1_SW (1U) //!< Bit field size in bits for RCM_SRS1_SW.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RCM_SRS1_SW field.
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#define BR_RCM_SRS1_SW (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_SW))
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#endif
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//@}
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/*!
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* @name Register RCM_SRS1, field MDM_AP[3] (RO)
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*
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* Indicates a reset has been caused by the host debugger system setting of the
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* System Reset Request bit in the MDM-AP Control Register.
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*
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* Values:
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* - 0 - Reset not caused by host debugger system setting of the System Reset
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* Request bit
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* - 1 - Reset caused by host debugger system setting of the System Reset
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* Request bit
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*/
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//@{
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#define BP_RCM_SRS1_MDM_AP (3U) //!< Bit position for RCM_SRS1_MDM_AP.
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#define BM_RCM_SRS1_MDM_AP (0x08U) //!< Bit mask for RCM_SRS1_MDM_AP.
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#define BS_RCM_SRS1_MDM_AP (1U) //!< Bit field size in bits for RCM_SRS1_MDM_AP.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RCM_SRS1_MDM_AP field.
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#define BR_RCM_SRS1_MDM_AP (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_MDM_AP))
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#endif
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//@}
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/*!
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* @name Register RCM_SRS1, field EZPT[4] (RO)
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*
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* Indicates a reset has been caused by EzPort receiving the RESET command while
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* the device is in EzPort mode.
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*
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* Values:
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* - 0 - Reset not caused by EzPort receiving the RESET command while the device
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* is in EzPort mode
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* - 1 - Reset caused by EzPort receiving the RESET command while the device is
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* in EzPort mode
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*/
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//@{
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#define BP_RCM_SRS1_EZPT (4U) //!< Bit position for RCM_SRS1_EZPT.
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#define BM_RCM_SRS1_EZPT (0x10U) //!< Bit mask for RCM_SRS1_EZPT.
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#define BS_RCM_SRS1_EZPT (1U) //!< Bit field size in bits for RCM_SRS1_EZPT.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the RCM_SRS1_EZPT field.
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#define BR_RCM_SRS1_EZPT (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_EZPT))
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#endif
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//@}
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/*!
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* @name Register RCM_SRS1, field SACKERR[5] (RO)
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*
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* Indicates that after an attempt to enter Stop mode, a reset has been caused
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* by a failure of one or more peripherals to acknowledge within approximately one
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* second to enter stop mode.
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*
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* Values:
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* - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter
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* stop mode
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* - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop
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* mode
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*/
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//@{
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#define BP_RCM_SRS1_SACKERR (5U) //!< Bit position for RCM_SRS1_SACKERR.
|
|
#define BM_RCM_SRS1_SACKERR (0x20U) //!< Bit mask for RCM_SRS1_SACKERR.
|
|
#define BS_RCM_SRS1_SACKERR (1U) //!< Bit field size in bits for RCM_SRS1_SACKERR.
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Read current value of the RCM_SRS1_SACKERR field.
|
|
#define BR_RCM_SRS1_SACKERR (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_SACKERR))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_RCM_RPFC - Reset Pin Filter Control register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_RCM_RPFC - Reset Pin Filter Control register (RW)
|
|
*
|
|
* Reset value: 0x00U
|
|
*
|
|
* The reset values of bits 2-0 are for Chip POR only. They are unaffected by
|
|
* other reset types. The bus clock filter is reset when disabled or when entering
|
|
* stop mode. The LPO filter is reset when disabled or when entering any low
|
|
* leakage stop mode .
|
|
*/
|
|
typedef union _hw_rcm_rpfc
|
|
{
|
|
uint8_t U;
|
|
struct _hw_rcm_rpfc_bitfields
|
|
{
|
|
uint8_t RSTFLTSRW : 2; //!< [1:0] Reset Pin Filter Select in Run and
|
|
//! Wait Modes
|
|
uint8_t RSTFLTSS : 1; //!< [2] Reset Pin Filter Select in Stop Mode
|
|
uint8_t RESERVED0 : 5; //!< [7:3]
|
|
} B;
|
|
} hw_rcm_rpfc_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire RCM_RPFC register
|
|
*/
|
|
//@{
|
|
#define HW_RCM_RPFC_ADDR (REGS_RCM_BASE + 0x4U)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_RCM_RPFC (*(__IO hw_rcm_rpfc_t *) HW_RCM_RPFC_ADDR)
|
|
#define HW_RCM_RPFC_RD() (HW_RCM_RPFC.U)
|
|
#define HW_RCM_RPFC_WR(v) (HW_RCM_RPFC.U = (v))
|
|
#define HW_RCM_RPFC_SET(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() | (v)))
|
|
#define HW_RCM_RPFC_CLR(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() & ~(v)))
|
|
#define HW_RCM_RPFC_TOG(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* Constants & macros for individual RCM_RPFC bitfields
|
|
*/
|
|
|
|
/*!
|
|
* @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
|
|
*
|
|
* Selects how the reset pin filter is enabled in run and wait modes.
|
|
*
|
|
* Values:
|
|
* - 00 - All filtering disabled
|
|
* - 01 - Bus clock filter enabled for normal operation
|
|
* - 10 - LPO clock filter enabled for normal operation
|
|
* - 11 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_RCM_RPFC_RSTFLTSRW (0U) //!< Bit position for RCM_RPFC_RSTFLTSRW.
|
|
#define BM_RCM_RPFC_RSTFLTSRW (0x03U) //!< Bit mask for RCM_RPFC_RSTFLTSRW.
|
|
#define BS_RCM_RPFC_RSTFLTSRW (2U) //!< Bit field size in bits for RCM_RPFC_RSTFLTSRW.
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Read current value of the RCM_RPFC_RSTFLTSRW field.
|
|
#define BR_RCM_RPFC_RSTFLTSRW (HW_RCM_RPFC.B.RSTFLTSRW)
|
|
#endif
|
|
|
|
//! @brief Format value for bitfield RCM_RPFC_RSTFLTSRW.
|
|
#define BF_RCM_RPFC_RSTFLTSRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFC_RSTFLTSRW), uint8_t) & BM_RCM_RPFC_RSTFLTSRW)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the RSTFLTSRW field to a new value.
|
|
#define BW_RCM_RPFC_RSTFLTSRW(v) (HW_RCM_RPFC_WR((HW_RCM_RPFC_RD() & ~BM_RCM_RPFC_RSTFLTSRW) | BF_RCM_RPFC_RSTFLTSRW(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*!
|
|
* @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
|
|
*
|
|
* Selects how the reset pin filter is enabled in Stop and VLPS modes
|
|
*
|
|
* Values:
|
|
* - 0 - All filtering disabled
|
|
* - 1 - LPO clock filter enabled
|
|
*/
|
|
//@{
|
|
#define BP_RCM_RPFC_RSTFLTSS (2U) //!< Bit position for RCM_RPFC_RSTFLTSS.
|
|
#define BM_RCM_RPFC_RSTFLTSS (0x04U) //!< Bit mask for RCM_RPFC_RSTFLTSS.
|
|
#define BS_RCM_RPFC_RSTFLTSS (1U) //!< Bit field size in bits for RCM_RPFC_RSTFLTSS.
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Read current value of the RCM_RPFC_RSTFLTSS field.
|
|
#define BR_RCM_RPFC_RSTFLTSS (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR, BP_RCM_RPFC_RSTFLTSS))
|
|
#endif
|
|
|
|
//! @brief Format value for bitfield RCM_RPFC_RSTFLTSS.
|
|
#define BF_RCM_RPFC_RSTFLTSS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFC_RSTFLTSS), uint8_t) & BM_RCM_RPFC_RSTFLTSS)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the RSTFLTSS field to a new value.
|
|
#define BW_RCM_RPFC_RSTFLTSS(v) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR, BP_RCM_RPFC_RSTFLTSS) = (v))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_RCM_RPFW - Reset Pin Filter Width register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_RCM_RPFW - Reset Pin Filter Width register (RW)
|
|
*
|
|
* Reset value: 0x00U
|
|
*
|
|
* The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
|
|
* They are unaffected by other reset types.
|
|
*/
|
|
typedef union _hw_rcm_rpfw
|
|
{
|
|
uint8_t U;
|
|
struct _hw_rcm_rpfw_bitfields
|
|
{
|
|
uint8_t RSTFLTSEL : 5; //!< [4:0] Reset Pin Filter Bus Clock Select
|
|
uint8_t RESERVED0 : 3; //!< [7:5]
|
|
} B;
|
|
} hw_rcm_rpfw_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire RCM_RPFW register
|
|
*/
|
|
//@{
|
|
#define HW_RCM_RPFW_ADDR (REGS_RCM_BASE + 0x5U)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_RCM_RPFW (*(__IO hw_rcm_rpfw_t *) HW_RCM_RPFW_ADDR)
|
|
#define HW_RCM_RPFW_RD() (HW_RCM_RPFW.U)
|
|
#define HW_RCM_RPFW_WR(v) (HW_RCM_RPFW.U = (v))
|
|
#define HW_RCM_RPFW_SET(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() | (v)))
|
|
#define HW_RCM_RPFW_CLR(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() & ~(v)))
|
|
#define HW_RCM_RPFW_TOG(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* Constants & macros for individual RCM_RPFW bitfields
|
|
*/
|
|
|
|
/*!
|
|
* @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
|
|
*
|
|
* Selects the reset pin bus clock filter width.
|
|
*
|
|
* Values:
|
|
* - 00000 - Bus clock filter count is 1
|
|
* - 00001 - Bus clock filter count is 2
|
|
* - 00010 - Bus clock filter count is 3
|
|
* - 00011 - Bus clock filter count is 4
|
|
* - 00100 - Bus clock filter count is 5
|
|
* - 00101 - Bus clock filter count is 6
|
|
* - 00110 - Bus clock filter count is 7
|
|
* - 00111 - Bus clock filter count is 8
|
|
* - 01000 - Bus clock filter count is 9
|
|
* - 01001 - Bus clock filter count is 10
|
|
* - 01010 - Bus clock filter count is 11
|
|
* - 01011 - Bus clock filter count is 12
|
|
* - 01100 - Bus clock filter count is 13
|
|
* - 01101 - Bus clock filter count is 14
|
|
* - 01110 - Bus clock filter count is 15
|
|
* - 01111 - Bus clock filter count is 16
|
|
* - 10000 - Bus clock filter count is 17
|
|
* - 10001 - Bus clock filter count is 18
|
|
* - 10010 - Bus clock filter count is 19
|
|
* - 10011 - Bus clock filter count is 20
|
|
* - 10100 - Bus clock filter count is 21
|
|
* - 10101 - Bus clock filter count is 22
|
|
* - 10110 - Bus clock filter count is 23
|
|
* - 10111 - Bus clock filter count is 24
|
|
* - 11000 - Bus clock filter count is 25
|
|
* - 11001 - Bus clock filter count is 26
|
|
* - 11010 - Bus clock filter count is 27
|
|
* - 11011 - Bus clock filter count is 28
|
|
* - 11100 - Bus clock filter count is 29
|
|
* - 11101 - Bus clock filter count is 30
|
|
* - 11110 - Bus clock filter count is 31
|
|
* - 11111 - Bus clock filter count is 32
|
|
*/
|
|
//@{
|
|
#define BP_RCM_RPFW_RSTFLTSEL (0U) //!< Bit position for RCM_RPFW_RSTFLTSEL.
|
|
#define BM_RCM_RPFW_RSTFLTSEL (0x1FU) //!< Bit mask for RCM_RPFW_RSTFLTSEL.
|
|
#define BS_RCM_RPFW_RSTFLTSEL (5U) //!< Bit field size in bits for RCM_RPFW_RSTFLTSEL.
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Read current value of the RCM_RPFW_RSTFLTSEL field.
|
|
#define BR_RCM_RPFW_RSTFLTSEL (HW_RCM_RPFW.B.RSTFLTSEL)
|
|
#endif
|
|
|
|
//! @brief Format value for bitfield RCM_RPFW_RSTFLTSEL.
|
|
#define BF_RCM_RPFW_RSTFLTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFW_RSTFLTSEL), uint8_t) & BM_RCM_RPFW_RSTFLTSEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the RSTFLTSEL field to a new value.
|
|
#define BW_RCM_RPFW_RSTFLTSEL(v) (HW_RCM_RPFW_WR((HW_RCM_RPFW_RD() & ~BM_RCM_RPFW_RSTFLTSEL) | BF_RCM_RPFW_RSTFLTSEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_RCM_MR - Mode Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_RCM_MR - Mode Register (RO)
|
|
*
|
|
* Reset value: 0x00U
|
|
*
|
|
* This register includes read-only status flags to indicate the state of the
|
|
* mode pins during the last Chip Reset.
|
|
*/
|
|
typedef union _hw_rcm_mr
|
|
{
|
|
uint8_t U;
|
|
struct _hw_rcm_mr_bitfields
|
|
{
|
|
uint8_t RESERVED0 : 1; //!< [0]
|
|
uint8_t EZP_MS : 1; //!< [1] EZP_MS_B pin state
|
|
uint8_t RESERVED1 : 6; //!< [7:2]
|
|
} B;
|
|
} hw_rcm_mr_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire RCM_MR register
|
|
*/
|
|
//@{
|
|
#define HW_RCM_MR_ADDR (REGS_RCM_BASE + 0x7U)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_RCM_MR (*(__I hw_rcm_mr_t *) HW_RCM_MR_ADDR)
|
|
#define HW_RCM_MR_RD() (HW_RCM_MR.U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* Constants & macros for individual RCM_MR bitfields
|
|
*/
|
|
|
|
/*!
|
|
* @name Register RCM_MR, field EZP_MS[1] (RO)
|
|
*
|
|
* Reflects the state of the EZP_MS pin during the last Chip Reset
|
|
*
|
|
* Values:
|
|
* - 0 - Pin deasserted (logic 1)
|
|
* - 1 - Pin asserted (logic 0)
|
|
*/
|
|
//@{
|
|
#define BP_RCM_MR_EZP_MS (1U) //!< Bit position for RCM_MR_EZP_MS.
|
|
#define BM_RCM_MR_EZP_MS (0x02U) //!< Bit mask for RCM_MR_EZP_MS.
|
|
#define BS_RCM_MR_EZP_MS (1U) //!< Bit field size in bits for RCM_MR_EZP_MS.
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Read current value of the RCM_MR_EZP_MS field.
|
|
#define BR_RCM_MR_EZP_MS (BITBAND_ACCESS8(HW_RCM_MR_ADDR, BP_RCM_MR_EZP_MS))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// hw_rcm_t - module struct
|
|
//-------------------------------------------------------------------------------------------
|
|
/*!
|
|
* @brief All RCM module registers.
|
|
*/
|
|
#ifndef __LANGUAGE_ASM__
|
|
#pragma pack(1)
|
|
typedef struct _hw_rcm
|
|
{
|
|
__I hw_rcm_srs0_t SRS0; //!< [0x0] System Reset Status Register 0
|
|
__I hw_rcm_srs1_t SRS1; //!< [0x1] System Reset Status Register 1
|
|
uint8_t _reserved0[2];
|
|
__IO hw_rcm_rpfc_t RPFC; //!< [0x4] Reset Pin Filter Control register
|
|
__IO hw_rcm_rpfw_t RPFW; //!< [0x5] Reset Pin Filter Width register
|
|
uint8_t _reserved1[1];
|
|
__I hw_rcm_mr_t MR; //!< [0x7] Mode Register
|
|
} hw_rcm_t;
|
|
#pragma pack()
|
|
|
|
//! @brief Macro to access all RCM registers.
|
|
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
|
//! use the '&' operator, like <code>&HW_RCM</code>.
|
|
#define HW_RCM (*(hw_rcm_t *) REGS_RCM_BASE)
|
|
#endif
|
|
|
|
#endif // __HW_RCM_REGISTERS_H__
|
|
// v22/130726/0.9
|
|
// EOF
|