630 lines
24 KiB
C
630 lines
24 KiB
C
/*
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* Copyright (c) 2014, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*
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* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
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*
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* This file was generated automatically and any changes may be lost.
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*/
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#ifndef __HW_LPTMR_REGISTERS_H__
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#define __HW_LPTMR_REGISTERS_H__
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#include "regs.h"
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/*
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* MK64F12 LPTMR
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*
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* Low Power Timer
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*
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* Registers defined in this header file:
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* - HW_LPTMR_CSR - Low Power Timer Control Status Register
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* - HW_LPTMR_PSR - Low Power Timer Prescale Register
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* - HW_LPTMR_CMR - Low Power Timer Compare Register
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* - HW_LPTMR_CNR - Low Power Timer Counter Register
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*
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* - hw_lptmr_t - Struct containing all module registers.
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*/
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//! @name Module base addresses
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//@{
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#ifndef REGS_LPTMR_BASE
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#define HW_LPTMR_INSTANCE_COUNT (1U) //!< Number of instances of the LPTMR module.
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#define REGS_LPTMR_BASE (0x40040000U) //!< Base address for LPTMR0.
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_LPTMR_CSR - Low Power Timer Control Status Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_LPTMR_CSR - Low Power Timer Control Status Register (RW)
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*
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* Reset value: 0x00000000U
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*/
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typedef union _hw_lptmr_csr
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{
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uint32_t U;
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struct _hw_lptmr_csr_bitfields
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{
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uint32_t TEN : 1; //!< [0] Timer Enable
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uint32_t TMS : 1; //!< [1] Timer Mode Select
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uint32_t TFC : 1; //!< [2] Timer Free-Running Counter
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uint32_t TPP : 1; //!< [3] Timer Pin Polarity
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uint32_t TPS : 2; //!< [5:4] Timer Pin Select
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uint32_t TIE : 1; //!< [6] Timer Interrupt Enable
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uint32_t TCF : 1; //!< [7] Timer Compare Flag
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uint32_t RESERVED0 : 24; //!< [31:8]
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} B;
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} hw_lptmr_csr_t;
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#endif
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/*!
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* @name Constants and macros for entire LPTMR_CSR register
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*/
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//@{
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#define HW_LPTMR_CSR_ADDR (REGS_LPTMR_BASE + 0x0U)
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#ifndef __LANGUAGE_ASM__
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#define HW_LPTMR_CSR (*(__IO hw_lptmr_csr_t *) HW_LPTMR_CSR_ADDR)
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#define HW_LPTMR_CSR_RD() (HW_LPTMR_CSR.U)
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#define HW_LPTMR_CSR_WR(v) (HW_LPTMR_CSR.U = (v))
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#define HW_LPTMR_CSR_SET(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() | (v)))
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#define HW_LPTMR_CSR_CLR(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() & ~(v)))
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#define HW_LPTMR_CSR_TOG(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() ^ (v)))
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#endif
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//@}
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/*
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* Constants & macros for individual LPTMR_CSR bitfields
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*/
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/*!
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* @name Register LPTMR_CSR, field TEN[0] (RW)
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*
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* When TEN is clear, it resets the LPTMR internal logic, including the CNR and
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* TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
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* CSR[5:1] must not be altered.
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*
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* Values:
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* - 0 - LPTMR is disabled and internal logic is reset.
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* - 1 - LPTMR is enabled.
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*/
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//@{
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#define BP_LPTMR_CSR_TEN (0U) //!< Bit position for LPTMR_CSR_TEN.
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#define BM_LPTMR_CSR_TEN (0x00000001U) //!< Bit mask for LPTMR_CSR_TEN.
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#define BS_LPTMR_CSR_TEN (1U) //!< Bit field size in bits for LPTMR_CSR_TEN.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the LPTMR_CSR_TEN field.
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#define BR_LPTMR_CSR_TEN (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TEN))
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#endif
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//! @brief Format value for bitfield LPTMR_CSR_TEN.
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#define BF_LPTMR_CSR_TEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TEN), uint32_t) & BM_LPTMR_CSR_TEN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the TEN field to a new value.
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#define BW_LPTMR_CSR_TEN(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TEN) = (v))
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#endif
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//@}
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/*!
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* @name Register LPTMR_CSR, field TMS[1] (RW)
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*
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* Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
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* disabled.
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*
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* Values:
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* - 0 - Time Counter mode.
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* - 1 - Pulse Counter mode.
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*/
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//@{
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#define BP_LPTMR_CSR_TMS (1U) //!< Bit position for LPTMR_CSR_TMS.
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#define BM_LPTMR_CSR_TMS (0x00000002U) //!< Bit mask for LPTMR_CSR_TMS.
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#define BS_LPTMR_CSR_TMS (1U) //!< Bit field size in bits for LPTMR_CSR_TMS.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the LPTMR_CSR_TMS field.
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#define BR_LPTMR_CSR_TMS (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TMS))
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#endif
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//! @brief Format value for bitfield LPTMR_CSR_TMS.
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#define BF_LPTMR_CSR_TMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TMS), uint32_t) & BM_LPTMR_CSR_TMS)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the TMS field to a new value.
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#define BW_LPTMR_CSR_TMS(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TMS) = (v))
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#endif
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//@}
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/*!
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* @name Register LPTMR_CSR, field TFC[2] (RW)
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*
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* When clear, TFC configures the CNR to reset whenever TCF is set. When set,
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* TFC configures the CNR to reset on overflow. TFC must be altered only when the
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* LPTMR is disabled.
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*
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* Values:
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* - 0 - CNR is reset whenever TCF is set.
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* - 1 - CNR is reset on overflow.
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*/
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//@{
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#define BP_LPTMR_CSR_TFC (2U) //!< Bit position for LPTMR_CSR_TFC.
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#define BM_LPTMR_CSR_TFC (0x00000004U) //!< Bit mask for LPTMR_CSR_TFC.
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#define BS_LPTMR_CSR_TFC (1U) //!< Bit field size in bits for LPTMR_CSR_TFC.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the LPTMR_CSR_TFC field.
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#define BR_LPTMR_CSR_TFC (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TFC))
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#endif
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//! @brief Format value for bitfield LPTMR_CSR_TFC.
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#define BF_LPTMR_CSR_TFC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TFC), uint32_t) & BM_LPTMR_CSR_TFC)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the TFC field to a new value.
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#define BW_LPTMR_CSR_TFC(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TFC) = (v))
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#endif
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//@}
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/*!
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* @name Register LPTMR_CSR, field TPP[3] (RW)
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*
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* Configures the polarity of the input source in Pulse Counter mode. TPP must
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* be changed only when the LPTMR is disabled.
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*
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* Values:
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* - 0 - Pulse Counter input source is active-high, and the CNR will increment
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* on the rising-edge.
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* - 1 - Pulse Counter input source is active-low, and the CNR will increment on
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* the falling-edge.
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*/
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//@{
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#define BP_LPTMR_CSR_TPP (3U) //!< Bit position for LPTMR_CSR_TPP.
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#define BM_LPTMR_CSR_TPP (0x00000008U) //!< Bit mask for LPTMR_CSR_TPP.
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#define BS_LPTMR_CSR_TPP (1U) //!< Bit field size in bits for LPTMR_CSR_TPP.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the LPTMR_CSR_TPP field.
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#define BR_LPTMR_CSR_TPP (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TPP))
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#endif
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//! @brief Format value for bitfield LPTMR_CSR_TPP.
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#define BF_LPTMR_CSR_TPP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TPP), uint32_t) & BM_LPTMR_CSR_TPP)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the TPP field to a new value.
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#define BW_LPTMR_CSR_TPP(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TPP) = (v))
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#endif
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//@}
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/*!
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* @name Register LPTMR_CSR, field TPS[5:4] (RW)
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*
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* Configures the input source to be used in Pulse Counter mode. TPS must be
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* altered only when the LPTMR is disabled. The input connections vary by device.
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* See the chip configuration details for information on the connections to these
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* inputs.
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*
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* Values:
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* - 00 - Pulse counter input 0 is selected.
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* - 01 - Pulse counter input 1 is selected.
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* - 10 - Pulse counter input 2 is selected.
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* - 11 - Pulse counter input 3 is selected.
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*/
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//@{
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#define BP_LPTMR_CSR_TPS (4U) //!< Bit position for LPTMR_CSR_TPS.
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#define BM_LPTMR_CSR_TPS (0x00000030U) //!< Bit mask for LPTMR_CSR_TPS.
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#define BS_LPTMR_CSR_TPS (2U) //!< Bit field size in bits for LPTMR_CSR_TPS.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the LPTMR_CSR_TPS field.
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#define BR_LPTMR_CSR_TPS (HW_LPTMR_CSR.B.TPS)
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#endif
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//! @brief Format value for bitfield LPTMR_CSR_TPS.
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#define BF_LPTMR_CSR_TPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TPS), uint32_t) & BM_LPTMR_CSR_TPS)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the TPS field to a new value.
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#define BW_LPTMR_CSR_TPS(v) (HW_LPTMR_CSR_WR((HW_LPTMR_CSR_RD() & ~BM_LPTMR_CSR_TPS) | BF_LPTMR_CSR_TPS(v)))
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#endif
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//@}
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/*!
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* @name Register LPTMR_CSR, field TIE[6] (RW)
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*
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* When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
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*
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* Values:
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* - 0 - Timer interrupt disabled.
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* - 1 - Timer interrupt enabled.
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*/
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//@{
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#define BP_LPTMR_CSR_TIE (6U) //!< Bit position for LPTMR_CSR_TIE.
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#define BM_LPTMR_CSR_TIE (0x00000040U) //!< Bit mask for LPTMR_CSR_TIE.
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#define BS_LPTMR_CSR_TIE (1U) //!< Bit field size in bits for LPTMR_CSR_TIE.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the LPTMR_CSR_TIE field.
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#define BR_LPTMR_CSR_TIE (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TIE))
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#endif
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//! @brief Format value for bitfield LPTMR_CSR_TIE.
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#define BF_LPTMR_CSR_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TIE), uint32_t) & BM_LPTMR_CSR_TIE)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the TIE field to a new value.
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#define BW_LPTMR_CSR_TIE(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TIE) = (v))
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#endif
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//@}
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/*!
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* @name Register LPTMR_CSR, field TCF[7] (W1C)
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*
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* TCF is set when the LPTMR is enabled and the CNR equals the CMR and
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* increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
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*
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* Values:
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* - 0 - The value of CNR is not equal to CMR and increments.
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* - 1 - The value of CNR is equal to CMR and increments.
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*/
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//@{
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#define BP_LPTMR_CSR_TCF (7U) //!< Bit position for LPTMR_CSR_TCF.
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#define BM_LPTMR_CSR_TCF (0x00000080U) //!< Bit mask for LPTMR_CSR_TCF.
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#define BS_LPTMR_CSR_TCF (1U) //!< Bit field size in bits for LPTMR_CSR_TCF.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the LPTMR_CSR_TCF field.
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#define BR_LPTMR_CSR_TCF (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TCF))
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#endif
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//! @brief Format value for bitfield LPTMR_CSR_TCF.
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#define BF_LPTMR_CSR_TCF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TCF), uint32_t) & BM_LPTMR_CSR_TCF)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the TCF field to a new value.
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#define BW_LPTMR_CSR_TCF(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TCF) = (v))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_LPTMR_PSR - Low Power Timer Prescale Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_LPTMR_PSR - Low Power Timer Prescale Register (RW)
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*
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* Reset value: 0x00000000U
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*/
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typedef union _hw_lptmr_psr
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{
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uint32_t U;
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struct _hw_lptmr_psr_bitfields
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{
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uint32_t PCS : 2; //!< [1:0] Prescaler Clock Select
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uint32_t PBYP : 1; //!< [2] Prescaler Bypass
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uint32_t PRESCALE : 4; //!< [6:3] Prescale Value
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uint32_t RESERVED0 : 25; //!< [31:7]
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} B;
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} hw_lptmr_psr_t;
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#endif
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/*!
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* @name Constants and macros for entire LPTMR_PSR register
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*/
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//@{
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#define HW_LPTMR_PSR_ADDR (REGS_LPTMR_BASE + 0x4U)
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#ifndef __LANGUAGE_ASM__
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#define HW_LPTMR_PSR (*(__IO hw_lptmr_psr_t *) HW_LPTMR_PSR_ADDR)
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#define HW_LPTMR_PSR_RD() (HW_LPTMR_PSR.U)
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#define HW_LPTMR_PSR_WR(v) (HW_LPTMR_PSR.U = (v))
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#define HW_LPTMR_PSR_SET(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() | (v)))
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#define HW_LPTMR_PSR_CLR(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() & ~(v)))
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#define HW_LPTMR_PSR_TOG(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() ^ (v)))
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#endif
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//@}
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/*
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* Constants & macros for individual LPTMR_PSR bitfields
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*/
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/*!
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* @name Register LPTMR_PSR, field PCS[1:0] (RW)
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*
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* Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
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* be altered only when the LPTMR is disabled. The clock connections vary by
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* device. See the chip configuration details for information on the connections to
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* these inputs.
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*
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* Values:
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* - 00 - Prescaler/glitch filter clock 0 selected.
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* - 01 - Prescaler/glitch filter clock 1 selected.
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* - 10 - Prescaler/glitch filter clock 2 selected.
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* - 11 - Prescaler/glitch filter clock 3 selected.
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*/
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//@{
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#define BP_LPTMR_PSR_PCS (0U) //!< Bit position for LPTMR_PSR_PCS.
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#define BM_LPTMR_PSR_PCS (0x00000003U) //!< Bit mask for LPTMR_PSR_PCS.
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#define BS_LPTMR_PSR_PCS (2U) //!< Bit field size in bits for LPTMR_PSR_PCS.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the LPTMR_PSR_PCS field.
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#define BR_LPTMR_PSR_PCS (HW_LPTMR_PSR.B.PCS)
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#endif
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//! @brief Format value for bitfield LPTMR_PSR_PCS.
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#define BF_LPTMR_PSR_PCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PCS), uint32_t) & BM_LPTMR_PSR_PCS)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PCS field to a new value.
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#define BW_LPTMR_PSR_PCS(v) (HW_LPTMR_PSR_WR((HW_LPTMR_PSR_RD() & ~BM_LPTMR_PSR_PCS) | BF_LPTMR_PSR_PCS(v)))
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#endif
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//@}
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/*!
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* @name Register LPTMR_PSR, field PBYP[2] (RW)
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*
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* When PBYP is set, the selected prescaler clock in Time Counter mode or
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* selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
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* clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
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* must be altered only when the LPTMR is disabled.
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*
|
|
* Values:
|
|
* - 0 - Prescaler/glitch filter is enabled.
|
|
* - 1 - Prescaler/glitch filter is bypassed.
|
|
*/
|
|
//@{
|
|
#define BP_LPTMR_PSR_PBYP (2U) //!< Bit position for LPTMR_PSR_PBYP.
|
|
#define BM_LPTMR_PSR_PBYP (0x00000004U) //!< Bit mask for LPTMR_PSR_PBYP.
|
|
#define BS_LPTMR_PSR_PBYP (1U) //!< Bit field size in bits for LPTMR_PSR_PBYP.
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Read current value of the LPTMR_PSR_PBYP field.
|
|
#define BR_LPTMR_PSR_PBYP (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR, BP_LPTMR_PSR_PBYP))
|
|
#endif
|
|
|
|
//! @brief Format value for bitfield LPTMR_PSR_PBYP.
|
|
#define BF_LPTMR_PSR_PBYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PBYP), uint32_t) & BM_LPTMR_PSR_PBYP)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PBYP field to a new value.
|
|
#define BW_LPTMR_PSR_PBYP(v) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR, BP_LPTMR_PSR_PBYP) = (v))
|
|
#endif
|
|
//@}
|
|
|
|
/*!
|
|
* @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
|
|
*
|
|
* Configures the size of the Prescaler in Time Counter mode or width of the
|
|
* glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
|
|
* is disabled.
|
|
*
|
|
* Values:
|
|
* - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
|
|
* support this configuration.
|
|
* - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes
|
|
* change on input pin after 2 rising clock edges.
|
|
* - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes
|
|
* change on input pin after 4 rising clock edges.
|
|
* - 0011 - Prescaler divides the prescaler clock by 16; glitch filter
|
|
* recognizes change on input pin after 8 rising clock edges.
|
|
* - 0100 - Prescaler divides the prescaler clock by 32; glitch filter
|
|
* recognizes change on input pin after 16 rising clock edges.
|
|
* - 0101 - Prescaler divides the prescaler clock by 64; glitch filter
|
|
* recognizes change on input pin after 32 rising clock edges.
|
|
* - 0110 - Prescaler divides the prescaler clock by 128; glitch filter
|
|
* recognizes change on input pin after 64 rising clock edges.
|
|
* - 0111 - Prescaler divides the prescaler clock by 256; glitch filter
|
|
* recognizes change on input pin after 128 rising clock edges.
|
|
* - 1000 - Prescaler divides the prescaler clock by 512; glitch filter
|
|
* recognizes change on input pin after 256 rising clock edges.
|
|
* - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter
|
|
* recognizes change on input pin after 512 rising clock edges.
|
|
* - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter
|
|
* recognizes change on input pin after 1024 rising clock edges.
|
|
* - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter
|
|
* recognizes change on input pin after 2048 rising clock edges.
|
|
* - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter
|
|
* recognizes change on input pin after 4096 rising clock edges.
|
|
* - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
|
|
* recognizes change on input pin after 8192 rising clock edges.
|
|
* - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
|
|
* recognizes change on input pin after 16,384 rising clock edges.
|
|
* - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
|
|
* recognizes change on input pin after 32,768 rising clock edges.
|
|
*/
|
|
//@{
|
|
#define BP_LPTMR_PSR_PRESCALE (3U) //!< Bit position for LPTMR_PSR_PRESCALE.
|
|
#define BM_LPTMR_PSR_PRESCALE (0x00000078U) //!< Bit mask for LPTMR_PSR_PRESCALE.
|
|
#define BS_LPTMR_PSR_PRESCALE (4U) //!< Bit field size in bits for LPTMR_PSR_PRESCALE.
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Read current value of the LPTMR_PSR_PRESCALE field.
|
|
#define BR_LPTMR_PSR_PRESCALE (HW_LPTMR_PSR.B.PRESCALE)
|
|
#endif
|
|
|
|
//! @brief Format value for bitfield LPTMR_PSR_PRESCALE.
|
|
#define BF_LPTMR_PSR_PRESCALE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PRESCALE), uint32_t) & BM_LPTMR_PSR_PRESCALE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRESCALE field to a new value.
|
|
#define BW_LPTMR_PSR_PRESCALE(v) (HW_LPTMR_PSR_WR((HW_LPTMR_PSR_RD() & ~BM_LPTMR_PSR_PRESCALE) | BF_LPTMR_PSR_PRESCALE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_LPTMR_CMR - Low Power Timer Compare Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_LPTMR_CMR - Low Power Timer Compare Register (RW)
|
|
*
|
|
* Reset value: 0x00000000U
|
|
*/
|
|
typedef union _hw_lptmr_cmr
|
|
{
|
|
uint32_t U;
|
|
struct _hw_lptmr_cmr_bitfields
|
|
{
|
|
uint32_t COMPARE : 16; //!< [15:0] Compare Value
|
|
uint32_t RESERVED0 : 16; //!< [31:16]
|
|
} B;
|
|
} hw_lptmr_cmr_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire LPTMR_CMR register
|
|
*/
|
|
//@{
|
|
#define HW_LPTMR_CMR_ADDR (REGS_LPTMR_BASE + 0x8U)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_LPTMR_CMR (*(__IO hw_lptmr_cmr_t *) HW_LPTMR_CMR_ADDR)
|
|
#define HW_LPTMR_CMR_RD() (HW_LPTMR_CMR.U)
|
|
#define HW_LPTMR_CMR_WR(v) (HW_LPTMR_CMR.U = (v))
|
|
#define HW_LPTMR_CMR_SET(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() | (v)))
|
|
#define HW_LPTMR_CMR_CLR(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() & ~(v)))
|
|
#define HW_LPTMR_CMR_TOG(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* Constants & macros for individual LPTMR_CMR bitfields
|
|
*/
|
|
|
|
/*!
|
|
* @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
|
|
*
|
|
* When the LPTMR is enabled and the CNR equals the value in the CMR and
|
|
* increments, TCF is set and the hardware trigger asserts until the next time the CNR
|
|
* increments. If the CMR is 0, the hardware trigger will remain asserted until
|
|
* the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
|
|
* when TCF is set.
|
|
*/
|
|
//@{
|
|
#define BP_LPTMR_CMR_COMPARE (0U) //!< Bit position for LPTMR_CMR_COMPARE.
|
|
#define BM_LPTMR_CMR_COMPARE (0x0000FFFFU) //!< Bit mask for LPTMR_CMR_COMPARE.
|
|
#define BS_LPTMR_CMR_COMPARE (16U) //!< Bit field size in bits for LPTMR_CMR_COMPARE.
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Read current value of the LPTMR_CMR_COMPARE field.
|
|
#define BR_LPTMR_CMR_COMPARE (HW_LPTMR_CMR.B.COMPARE)
|
|
#endif
|
|
|
|
//! @brief Format value for bitfield LPTMR_CMR_COMPARE.
|
|
#define BF_LPTMR_CMR_COMPARE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CMR_COMPARE), uint32_t) & BM_LPTMR_CMR_COMPARE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COMPARE field to a new value.
|
|
#define BW_LPTMR_CMR_COMPARE(v) (HW_LPTMR_CMR_WR((HW_LPTMR_CMR_RD() & ~BM_LPTMR_CMR_COMPARE) | BF_LPTMR_CMR_COMPARE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_LPTMR_CNR - Low Power Timer Counter Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_LPTMR_CNR - Low Power Timer Counter Register (RW)
|
|
*
|
|
* Reset value: 0x00000000U
|
|
*/
|
|
typedef union _hw_lptmr_cnr
|
|
{
|
|
uint32_t U;
|
|
struct _hw_lptmr_cnr_bitfields
|
|
{
|
|
uint32_t COUNTER : 16; //!< [15:0] Counter Value
|
|
uint32_t RESERVED0 : 16; //!< [31:16]
|
|
} B;
|
|
} hw_lptmr_cnr_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire LPTMR_CNR register
|
|
*/
|
|
//@{
|
|
#define HW_LPTMR_CNR_ADDR (REGS_LPTMR_BASE + 0xCU)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_LPTMR_CNR (*(__IO hw_lptmr_cnr_t *) HW_LPTMR_CNR_ADDR)
|
|
#define HW_LPTMR_CNR_RD() (HW_LPTMR_CNR.U)
|
|
#define HW_LPTMR_CNR_WR(v) (HW_LPTMR_CNR.U = (v))
|
|
#define HW_LPTMR_CNR_SET(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() | (v)))
|
|
#define HW_LPTMR_CNR_CLR(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() & ~(v)))
|
|
#define HW_LPTMR_CNR_TOG(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* Constants & macros for individual LPTMR_CNR bitfields
|
|
*/
|
|
|
|
/*!
|
|
* @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
|
|
*/
|
|
//@{
|
|
#define BP_LPTMR_CNR_COUNTER (0U) //!< Bit position for LPTMR_CNR_COUNTER.
|
|
#define BM_LPTMR_CNR_COUNTER (0x0000FFFFU) //!< Bit mask for LPTMR_CNR_COUNTER.
|
|
#define BS_LPTMR_CNR_COUNTER (16U) //!< Bit field size in bits for LPTMR_CNR_COUNTER.
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Read current value of the LPTMR_CNR_COUNTER field.
|
|
#define BR_LPTMR_CNR_COUNTER (HW_LPTMR_CNR.B.COUNTER)
|
|
#endif
|
|
|
|
//! @brief Format value for bitfield LPTMR_CNR_COUNTER.
|
|
#define BF_LPTMR_CNR_COUNTER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CNR_COUNTER), uint32_t) & BM_LPTMR_CNR_COUNTER)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COUNTER field to a new value.
|
|
#define BW_LPTMR_CNR_COUNTER(v) (HW_LPTMR_CNR_WR((HW_LPTMR_CNR_RD() & ~BM_LPTMR_CNR_COUNTER) | BF_LPTMR_CNR_COUNTER(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// hw_lptmr_t - module struct
|
|
//-------------------------------------------------------------------------------------------
|
|
/*!
|
|
* @brief All LPTMR module registers.
|
|
*/
|
|
#ifndef __LANGUAGE_ASM__
|
|
#pragma pack(1)
|
|
typedef struct _hw_lptmr
|
|
{
|
|
__IO hw_lptmr_csr_t CSR; //!< [0x0] Low Power Timer Control Status Register
|
|
__IO hw_lptmr_psr_t PSR; //!< [0x4] Low Power Timer Prescale Register
|
|
__IO hw_lptmr_cmr_t CMR; //!< [0x8] Low Power Timer Compare Register
|
|
__IO hw_lptmr_cnr_t CNR; //!< [0xC] Low Power Timer Counter Register
|
|
} hw_lptmr_t;
|
|
#pragma pack()
|
|
|
|
//! @brief Macro to access all LPTMR registers.
|
|
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
|
//! use the '&' operator, like <code>&HW_LPTMR</code>.
|
|
#define HW_LPTMR (*(hw_lptmr_t *) REGS_LPTMR_BASE)
|
|
#endif
|
|
|
|
#endif // __HW_LPTMR_REGISTERS_H__
|
|
// v22/130726/0.9
|
|
// EOF
|