431 lines
15 KiB
C
431 lines
15 KiB
C
/*
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* Copyright (c) 2014, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*
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* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
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*
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* This file was generated automatically and any changes may be lost.
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*/
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#ifndef __HW_EWM_REGISTERS_H__
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#define __HW_EWM_REGISTERS_H__
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#include "regs.h"
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/*
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* MK64F12 EWM
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*
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* External Watchdog Monitor
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*
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* Registers defined in this header file:
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* - HW_EWM_CTRL - Control Register
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* - HW_EWM_SERV - Service Register
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* - HW_EWM_CMPL - Compare Low Register
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* - HW_EWM_CMPH - Compare High Register
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*
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* - hw_ewm_t - Struct containing all module registers.
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*/
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//! @name Module base addresses
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//@{
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#ifndef REGS_EWM_BASE
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#define HW_EWM_INSTANCE_COUNT (1U) //!< Number of instances of the EWM module.
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#define REGS_EWM_BASE (0x40061000U) //!< Base address for EWM.
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_EWM_CTRL - Control Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_EWM_CTRL - Control Register (RW)
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*
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* Reset value: 0x00U
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*
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* The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
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* written once after a CPU reset. Modifying these bits more than once, generates
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* a bus transfer error.
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*/
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typedef union _hw_ewm_ctrl
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{
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uint8_t U;
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struct _hw_ewm_ctrl_bitfields
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{
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uint8_t EWMEN : 1; //!< [0] EWM enable.
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uint8_t ASSIN : 1; //!< [1] EWM_in's Assertion State Select.
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uint8_t INEN : 1; //!< [2] Input Enable.
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uint8_t INTEN : 1; //!< [3] Interrupt Enable.
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uint8_t RESERVED0 : 4; //!< [7:4]
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} B;
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} hw_ewm_ctrl_t;
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#endif
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/*!
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* @name Constants and macros for entire EWM_CTRL register
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*/
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//@{
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#define HW_EWM_CTRL_ADDR (REGS_EWM_BASE + 0x0U)
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#ifndef __LANGUAGE_ASM__
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#define HW_EWM_CTRL (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR)
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#define HW_EWM_CTRL_RD() (HW_EWM_CTRL.U)
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#define HW_EWM_CTRL_WR(v) (HW_EWM_CTRL.U = (v))
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#define HW_EWM_CTRL_SET(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() | (v)))
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#define HW_EWM_CTRL_CLR(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() & ~(v)))
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#define HW_EWM_CTRL_TOG(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() ^ (v)))
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#endif
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//@}
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/*
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* Constants & macros for individual EWM_CTRL bitfields
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*/
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/*!
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* @name Register EWM_CTRL, field EWMEN[0] (RW)
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*
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* This bit when set, enables the EWM module. This resets the EWM counter to
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* zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
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* therefore it cannot be enabled until a reset occurs, due to the write-once
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* nature of this bit.
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*/
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//@{
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#define BP_EWM_CTRL_EWMEN (0U) //!< Bit position for EWM_CTRL_EWMEN.
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#define BM_EWM_CTRL_EWMEN (0x01U) //!< Bit mask for EWM_CTRL_EWMEN.
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#define BS_EWM_CTRL_EWMEN (1U) //!< Bit field size in bits for EWM_CTRL_EWMEN.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the EWM_CTRL_EWMEN field.
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#define BR_EWM_CTRL_EWMEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_EWMEN))
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#endif
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//! @brief Format value for bitfield EWM_CTRL_EWMEN.
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#define BF_EWM_CTRL_EWMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_EWMEN), uint8_t) & BM_EWM_CTRL_EWMEN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the EWMEN field to a new value.
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#define BW_EWM_CTRL_EWMEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_EWMEN) = (v))
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#endif
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//@}
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/*!
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* @name Register EWM_CTRL, field ASSIN[1] (RW)
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*
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* Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
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* inverts the assert state to a logic one.
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*/
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//@{
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#define BP_EWM_CTRL_ASSIN (1U) //!< Bit position for EWM_CTRL_ASSIN.
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#define BM_EWM_CTRL_ASSIN (0x02U) //!< Bit mask for EWM_CTRL_ASSIN.
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#define BS_EWM_CTRL_ASSIN (1U) //!< Bit field size in bits for EWM_CTRL_ASSIN.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the EWM_CTRL_ASSIN field.
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#define BR_EWM_CTRL_ASSIN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_ASSIN))
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#endif
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//! @brief Format value for bitfield EWM_CTRL_ASSIN.
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#define BF_EWM_CTRL_ASSIN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_ASSIN), uint8_t) & BM_EWM_CTRL_ASSIN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the ASSIN field to a new value.
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#define BW_EWM_CTRL_ASSIN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_ASSIN) = (v))
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#endif
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//@}
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/*!
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* @name Register EWM_CTRL, field INEN[2] (RW)
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*
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* This bit when set, enables the EWM_in port.
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*/
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//@{
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#define BP_EWM_CTRL_INEN (2U) //!< Bit position for EWM_CTRL_INEN.
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#define BM_EWM_CTRL_INEN (0x04U) //!< Bit mask for EWM_CTRL_INEN.
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#define BS_EWM_CTRL_INEN (1U) //!< Bit field size in bits for EWM_CTRL_INEN.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the EWM_CTRL_INEN field.
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#define BR_EWM_CTRL_INEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INEN))
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#endif
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//! @brief Format value for bitfield EWM_CTRL_INEN.
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#define BF_EWM_CTRL_INEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_INEN), uint8_t) & BM_EWM_CTRL_INEN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the INEN field to a new value.
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#define BW_EWM_CTRL_INEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INEN) = (v))
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#endif
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//@}
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/*!
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* @name Register EWM_CTRL, field INTEN[3] (RW)
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*
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* This bit when set and EWM_out is asserted, an interrupt request is generated.
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* To de-assert interrupt request, user should clear this bit by writing 0.
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*/
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//@{
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#define BP_EWM_CTRL_INTEN (3U) //!< Bit position for EWM_CTRL_INTEN.
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#define BM_EWM_CTRL_INTEN (0x08U) //!< Bit mask for EWM_CTRL_INTEN.
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#define BS_EWM_CTRL_INTEN (1U) //!< Bit field size in bits for EWM_CTRL_INTEN.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the EWM_CTRL_INTEN field.
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#define BR_EWM_CTRL_INTEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INTEN))
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#endif
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//! @brief Format value for bitfield EWM_CTRL_INTEN.
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#define BF_EWM_CTRL_INTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_INTEN), uint8_t) & BM_EWM_CTRL_INTEN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the INTEN field to a new value.
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#define BW_EWM_CTRL_INTEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INTEN) = (v))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_EWM_SERV - Service Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_EWM_SERV - Service Register (WORZ)
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*
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* Reset value: 0x00U
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*
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* The SERV register provides the interface from the CPU to the EWM module. It
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* is write-only and reads of this register return zero.
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*/
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typedef union _hw_ewm_serv
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{
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uint8_t U;
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struct _hw_ewm_serv_bitfields
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{
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uint8_t SERVICE : 8; //!< [7:0]
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} B;
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} hw_ewm_serv_t;
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#endif
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/*!
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* @name Constants and macros for entire EWM_SERV register
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*/
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//@{
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#define HW_EWM_SERV_ADDR (REGS_EWM_BASE + 0x1U)
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#ifndef __LANGUAGE_ASM__
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#define HW_EWM_SERV (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR)
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#define HW_EWM_SERV_RD() (HW_EWM_SERV.U)
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#define HW_EWM_SERV_WR(v) (HW_EWM_SERV.U = (v))
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#endif
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//@}
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/*
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* Constants & macros for individual EWM_SERV bitfields
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*/
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/*!
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* @name Register EWM_SERV, field SERVICE[7:0] (WORZ)
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*
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* The EWM service mechanism requires the CPU to write two values to the SERV
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* register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The
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* EWM service is illegal if either of the following conditions is true. The
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* first or second data byte is not written correctly. The second data byte is not
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* written within a fixed number of peripheral bus cycles of the first data byte.
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* This fixed number of cycles is called EWM_service_time.
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*/
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//@{
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#define BP_EWM_SERV_SERVICE (0U) //!< Bit position for EWM_SERV_SERVICE.
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#define BM_EWM_SERV_SERVICE (0xFFU) //!< Bit mask for EWM_SERV_SERVICE.
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#define BS_EWM_SERV_SERVICE (8U) //!< Bit field size in bits for EWM_SERV_SERVICE.
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//! @brief Format value for bitfield EWM_SERV_SERVICE.
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#define BF_EWM_SERV_SERVICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_SERV_SERVICE), uint8_t) & BM_EWM_SERV_SERVICE)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the SERVICE field to a new value.
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#define BW_EWM_SERV_SERVICE(v) (HW_EWM_SERV_WR(v))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_EWM_CMPL - Compare Low Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_EWM_CMPL - Compare Low Register (RW)
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*
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* Reset value: 0x00U
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*
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* The CMPL register is reset to zero after a CPU reset. This provides no
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* minimum time for the CPU to service the EWM counter. This register can be written
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* only once after a CPU reset. Writing this register more than once generates a
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* bus transfer error.
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*/
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typedef union _hw_ewm_cmpl
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{
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uint8_t U;
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struct _hw_ewm_cmpl_bitfields
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{
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uint8_t COMPAREL : 8; //!< [7:0]
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} B;
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} hw_ewm_cmpl_t;
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#endif
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/*!
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* @name Constants and macros for entire EWM_CMPL register
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*/
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//@{
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#define HW_EWM_CMPL_ADDR (REGS_EWM_BASE + 0x2U)
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#ifndef __LANGUAGE_ASM__
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#define HW_EWM_CMPL (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR)
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#define HW_EWM_CMPL_RD() (HW_EWM_CMPL.U)
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#define HW_EWM_CMPL_WR(v) (HW_EWM_CMPL.U = (v))
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#define HW_EWM_CMPL_SET(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() | (v)))
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#define HW_EWM_CMPL_CLR(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() & ~(v)))
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#define HW_EWM_CMPL_TOG(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() ^ (v)))
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#endif
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//@}
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/*
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* Constants & macros for individual EWM_CMPL bitfields
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*/
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/*!
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* @name Register EWM_CMPL, field COMPAREL[7:0] (RW)
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*
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* To prevent runaway code from changing this field, software should write to
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* this field after a CPU reset even if the (default) minimum service time is
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* required.
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*/
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//@{
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#define BP_EWM_CMPL_COMPAREL (0U) //!< Bit position for EWM_CMPL_COMPAREL.
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#define BM_EWM_CMPL_COMPAREL (0xFFU) //!< Bit mask for EWM_CMPL_COMPAREL.
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#define BS_EWM_CMPL_COMPAREL (8U) //!< Bit field size in bits for EWM_CMPL_COMPAREL.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the EWM_CMPL_COMPAREL field.
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#define BR_EWM_CMPL_COMPAREL (HW_EWM_CMPL.U)
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#endif
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//! @brief Format value for bitfield EWM_CMPL_COMPAREL.
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#define BF_EWM_CMPL_COMPAREL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CMPL_COMPAREL), uint8_t) & BM_EWM_CMPL_COMPAREL)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COMPAREL field to a new value.
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#define BW_EWM_CMPL_COMPAREL(v) (HW_EWM_CMPL_WR(v))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_EWM_CMPH - Compare High Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_EWM_CMPH - Compare High Register (RW)
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*
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* Reset value: 0xFFU
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*
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* The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
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* of 256 clocks time, for the CPU to service the EWM counter. This register can
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* be written only once after a CPU reset. Writing this register more than once
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* generates a bus transfer error. The valid values for CMPH are up to 0xFE
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* because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
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* if EWM counter is greater than CMPH.
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*/
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typedef union _hw_ewm_cmph
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{
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uint8_t U;
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struct _hw_ewm_cmph_bitfields
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{
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uint8_t COMPAREH : 8; //!< [7:0]
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} B;
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} hw_ewm_cmph_t;
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#endif
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/*!
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* @name Constants and macros for entire EWM_CMPH register
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*/
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//@{
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#define HW_EWM_CMPH_ADDR (REGS_EWM_BASE + 0x3U)
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#ifndef __LANGUAGE_ASM__
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#define HW_EWM_CMPH (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR)
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#define HW_EWM_CMPH_RD() (HW_EWM_CMPH.U)
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#define HW_EWM_CMPH_WR(v) (HW_EWM_CMPH.U = (v))
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#define HW_EWM_CMPH_SET(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() | (v)))
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#define HW_EWM_CMPH_CLR(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() & ~(v)))
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#define HW_EWM_CMPH_TOG(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() ^ (v)))
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#endif
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//@}
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/*
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* Constants & macros for individual EWM_CMPH bitfields
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*/
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/*!
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* @name Register EWM_CMPH, field COMPAREH[7:0] (RW)
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*
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* To prevent runaway code from changing this field, software should write to
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* this field after a CPU reset even if the (default) maximum service time is
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* required.
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*/
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//@{
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#define BP_EWM_CMPH_COMPAREH (0U) //!< Bit position for EWM_CMPH_COMPAREH.
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#define BM_EWM_CMPH_COMPAREH (0xFFU) //!< Bit mask for EWM_CMPH_COMPAREH.
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#define BS_EWM_CMPH_COMPAREH (8U) //!< Bit field size in bits for EWM_CMPH_COMPAREH.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the EWM_CMPH_COMPAREH field.
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#define BR_EWM_CMPH_COMPAREH (HW_EWM_CMPH.U)
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#endif
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//! @brief Format value for bitfield EWM_CMPH_COMPAREH.
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#define BF_EWM_CMPH_COMPAREH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CMPH_COMPAREH), uint8_t) & BM_EWM_CMPH_COMPAREH)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COMPAREH field to a new value.
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#define BW_EWM_CMPH_COMPAREH(v) (HW_EWM_CMPH_WR(v))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// hw_ewm_t - module struct
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//-------------------------------------------------------------------------------------------
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/*!
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* @brief All EWM module registers.
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*/
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#ifndef __LANGUAGE_ASM__
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#pragma pack(1)
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typedef struct _hw_ewm
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{
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__IO hw_ewm_ctrl_t CTRL; //!< [0x0] Control Register
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__O hw_ewm_serv_t SERV; //!< [0x1] Service Register
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__IO hw_ewm_cmpl_t CMPL; //!< [0x2] Compare Low Register
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__IO hw_ewm_cmph_t CMPH; //!< [0x3] Compare High Register
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} hw_ewm_t;
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#pragma pack()
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//! @brief Macro to access all EWM registers.
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//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
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//! use the '&' operator, like <code>&HW_EWM</code>.
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#define HW_EWM (*(hw_ewm_t *) REGS_EWM_BASE)
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#endif
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#endif // __HW_EWM_REGISTERS_H__
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// v22/130726/0.9
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// EOF
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