221 lines
8.4 KiB
C
221 lines
8.4 KiB
C
/*
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* Copyright (c) 2014, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*
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* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
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*
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* This file was generated automatically and any changes may be lost.
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*/
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#ifndef __HW_DMAMUX_REGISTERS_H__
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#define __HW_DMAMUX_REGISTERS_H__
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#include "regs.h"
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/*
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* MK64F12 DMAMUX
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*
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* DMA channel multiplexor
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*
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* Registers defined in this header file:
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* - HW_DMAMUX_CHCFGn - Channel Configuration register
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*
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* - hw_dmamux_t - Struct containing all module registers.
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*/
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//! @name Module base addresses
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//@{
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#ifndef REGS_DMAMUX_BASE
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#define HW_DMAMUX_INSTANCE_COUNT (1U) //!< Number of instances of the DMAMUX module.
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#define HW_DMAMUX0 (0U) //!< Instance number for DMAMUX.
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#define REGS_DMAMUX0_BASE (0x40021000U) //!< Base address for DMAMUX.
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//! @brief Table of base addresses for DMAMUX instances.
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static const uint32_t __g_regs_DMAMUX_base_addresses[] = {
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REGS_DMAMUX0_BASE,
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};
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//! @brief Get the base address of DMAMUX by instance number.
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//! @param x DMAMUX instance number, from 0 through 0.
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#define REGS_DMAMUX_BASE(x) (__g_regs_DMAMUX_base_addresses[(x)])
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//! @brief Get the instance number given a base address.
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//! @param b Base address for an instance of DMAMUX.
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#define REGS_DMAMUX_INSTANCE(b) ((b) == REGS_DMAMUX0_BASE ? HW_DMAMUX0 : 0)
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_DMAMUX_CHCFGn - Channel Configuration register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
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*
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* Reset value: 0x00U
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*
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* Each of the DMA channels can be independently enabled/disabled and associated
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* with one of the DMA slots (peripheral slots or always-on slots) in the
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* system. Setting multiple CHCFG registers with the same source value will result in
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* unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
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* Before changing the trigger or source settings, a DMA channel must be disabled
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* via CHCFGn[ENBL].
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*/
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typedef union _hw_dmamux_chcfgn
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{
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uint8_t U;
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struct _hw_dmamux_chcfgn_bitfields
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{
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uint8_t SOURCE : 6; //!< [5:0] DMA Channel Source (Slot)
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uint8_t TRIG : 1; //!< [6] DMA Channel Trigger Enable
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uint8_t ENBL : 1; //!< [7] DMA Channel Enable
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} B;
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} hw_dmamux_chcfgn_t;
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#endif
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/*!
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* @name Constants and macros for entire DMAMUX_CHCFGn register
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*/
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//@{
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#define HW_DMAMUX_CHCFGn_COUNT (16U)
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#define HW_DMAMUX_CHCFGn_ADDR(x, n) (REGS_DMAMUX_BASE(x) + 0x0U + (0x1U * n))
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#ifndef __LANGUAGE_ASM__
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#define HW_DMAMUX_CHCFGn(x, n) (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n))
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#define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U)
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#define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v))
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#define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) | (v)))
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#define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v)))
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#define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^ (v)))
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#endif
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//@}
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/*
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* Constants & macros for individual DMAMUX_CHCFGn bitfields
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*/
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/*!
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* @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
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*
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* Specifies which DMA source, if any, is routed to a particular DMA channel.
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* See your device's chip configuration details for information about the
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* peripherals and their slot numbers.
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*/
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//@{
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#define BP_DMAMUX_CHCFGn_SOURCE (0U) //!< Bit position for DMAMUX_CHCFGn_SOURCE.
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#define BM_DMAMUX_CHCFGn_SOURCE (0x3FU) //!< Bit mask for DMAMUX_CHCFGn_SOURCE.
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#define BS_DMAMUX_CHCFGn_SOURCE (6U) //!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field.
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#define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE)
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#endif
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//! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE.
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#define BF_DMAMUX_CHCFGn_SOURCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_SOURCE), uint8_t) & BM_DMAMUX_CHCFGn_SOURCE)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the SOURCE field to a new value.
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#define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v)))
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#endif
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//@}
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/*!
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* @name Register DMAMUX_CHCFGn, field TRIG[6] (RW)
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*
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* Enables the periodic trigger capability for the triggered DMA channel.
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*
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* Values:
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* - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
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* DMA Channel will simply route the specified source to the DMA channel.
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* (Normal mode)
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* - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
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* DMAMUX is in Periodic Trigger mode.
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*/
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//@{
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#define BP_DMAMUX_CHCFGn_TRIG (6U) //!< Bit position for DMAMUX_CHCFGn_TRIG.
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#define BM_DMAMUX_CHCFGn_TRIG (0x40U) //!< Bit mask for DMAMUX_CHCFGn_TRIG.
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#define BS_DMAMUX_CHCFGn_TRIG (1U) //!< Bit field size in bits for DMAMUX_CHCFGn_TRIG.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the DMAMUX_CHCFGn_TRIG field.
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#define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG))
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#endif
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//! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG.
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#define BF_DMAMUX_CHCFGn_TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_TRIG), uint8_t) & BM_DMAMUX_CHCFGn_TRIG)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the TRIG field to a new value.
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#define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v))
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#endif
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//@}
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/*!
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* @name Register DMAMUX_CHCFGn, field ENBL[7] (RW)
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*
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* Enables the DMA channel.
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*
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* Values:
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* - 0 - DMA channel is disabled. This mode is primarily used during
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* configuration of the DMAMux. The DMA has separate channel enables/disables, which
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* should be used to disable or reconfigure a DMA channel.
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* - 1 - DMA channel is enabled
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*/
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//@{
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#define BP_DMAMUX_CHCFGn_ENBL (7U) //!< Bit position for DMAMUX_CHCFGn_ENBL.
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#define BM_DMAMUX_CHCFGn_ENBL (0x80U) //!< Bit mask for DMAMUX_CHCFGn_ENBL.
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#define BS_DMAMUX_CHCFGn_ENBL (1U) //!< Bit field size in bits for DMAMUX_CHCFGn_ENBL.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the DMAMUX_CHCFGn_ENBL field.
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#define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL))
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#endif
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//! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL.
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#define BF_DMAMUX_CHCFGn_ENBL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_ENBL), uint8_t) & BM_DMAMUX_CHCFGn_ENBL)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the ENBL field to a new value.
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#define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// hw_dmamux_t - module struct
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//-------------------------------------------------------------------------------------------
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/*!
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* @brief All DMAMUX module registers.
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*/
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#ifndef __LANGUAGE_ASM__
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#pragma pack(1)
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typedef struct _hw_dmamux
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{
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__IO hw_dmamux_chcfgn_t CHCFGn[16]; //!< [0x0] Channel Configuration register
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} hw_dmamux_t;
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#pragma pack()
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//! @brief Macro to access all DMAMUX registers.
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//! @param x DMAMUX instance number.
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//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
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//! use the '&' operator, like <code>&HW_DMAMUX(0)</code>.
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#define HW_DMAMUX(x) (*(hw_dmamux_t *) REGS_DMAMUX_BASE(x))
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#endif
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#endif // __HW_DMAMUX_REGISTERS_H__
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// v22/130726/0.9
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// EOF
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