184 lines
7.3 KiB
C
184 lines
7.3 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FSL_PHY_H_
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#define _FSL_PHY_H_
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#include "fsl_enet.h"
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/*!
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* @addtogroup phy_driver
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief PHY driver version */
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#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
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/*! @brief Defines the PHY registers. */
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#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */
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#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */
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#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */
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#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */
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#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
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#define PHY_SEPCIAL_CONTROL_REG 0x1FU /*!< The PHY control two register. */
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#define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/
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/*! @brief Defines the mask flag in basic control register. */
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#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */
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#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
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#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */
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#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */
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#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
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#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
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/*!@brief Defines the mask flag of operation mode in special control register*/
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#define PHY_SPECIALCTL_AUTONEGDONE_MASK 0x1000U /*!< The PHY auto-negotiation complete mask. */
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#define PHY_SPECIALCTL_DUPLEX_MASK 0x0010U /*!< The PHY duplex mask. */
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#define PHY_SPECIALCTL_100SPEED_MASK 0x0008U /*!< The PHY speed mask. */
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#define PHY_SPECIALCTL_10SPEED_MASK 0x0004U /*!< The PHY speed mask. */
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#define PHY_SPECIALCTL_SPEEDUPLX_MASK 0x001cU /*!< The PHY speed and duplex mask. */
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/*! @brief Defines the mask flag in basic status register. */
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#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
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/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
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#define PHY_ALL_CAPABLE_MASK 0x1e0U
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/*! @brief Defines the PHY status. */
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enum _phy_status
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{
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kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 0), /*!< ENET PHY SMI visit timeout. */
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};
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/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
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typedef enum _phy_speed {
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kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
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kPHY_Speed100M /*!< ENET PHY 100M speed. */
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} phy_speed_t;
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/*! @brief Defines the PHY link duplex. */
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typedef enum _phy_duplex {
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kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
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kPHY_FullDuplex /*!< ENET PHY full duplex. */
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} phy_duplex_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @name PHY Driver
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* @{
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*/
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/*!
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* @brief Initializes PHY.
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*
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* This function initialize the SMI interface and initialize PHY.
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* The SMI is the MII management interface between PHY and MAC, which should be
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* firstly initialized before any other operation for PHY.
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*
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* @param base ENET peripheral base address.
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* @param phyAddr The PHY address.
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* @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI.
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* @retval kStatus_Success PHY initialize success
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* @retval kStatus_Fail PHY initialize fail
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*/
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status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
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/*!
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* @brief PHY Write function. This function write data over the SMI to
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* the specified PHY register. This function is called by all PHY interfaces.
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*
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* @param base ENET peripheral base address.
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* @param phyAddr The PHY address.
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* @param phyReg The PHY register.
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* @param data The data written to the PHY register.
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* @retval kStatus_Success PHY write success
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* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
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*/
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status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
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/*!
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* @brief PHY Read function. This interface read data over the SMI from the
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* specified PHY register. This function is called by all PHY interfaces.
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*
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* @param base ENET peripheral base address.
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* @param phyAddr The PHY address.
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* @param phyReg The PHY register.
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* @param dataPtr The address to store the data read from the PHY register.
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* @retval kStatus_Success PHY read success
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* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
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*/
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status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
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/*!
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* @brief Gets the PHY link status.
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*
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* @param base ENET peripheral base address.
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* @param phyAddr The PHY address.
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* @param status The link up or down status of the PHY.
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* - true the link is up.
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* - false the link is down.
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* @retval kStatus_Success PHY get link status success
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* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
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*/
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status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status);
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/*!
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* @brief Gets the PHY link speed and duplex.
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*
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* @param base ENET peripheral base address.
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* @param phyAddr The PHY address.
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* @param speed The address of PHY link speed.
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* @param duplex The link duplex of PHY.
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* @retval kStatus_Success PHY get link speed and duplex success
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* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
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*/
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status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex);
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/* @} */
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#if defined(__cplusplus)
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}
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#endif
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/*! @}*/
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#endif /* _FSL_PHY_H_ */
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