255 lines
10 KiB
C
255 lines
10 KiB
C
/*
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* File : drv_clock.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2017, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2018-02-08 RT-Thread the first version
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*/
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#ifndef __DRV_CLOCK_H__
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#define __DRV_CLOCK_H__
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/* PLL state */
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#define PLL_ENBALE (0x1)
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#define PLL_STABLE (0x2)
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/* Clock source selection */
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#define CLK_LOSC_SRC (0x00)
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#define CLK_OSC24M_SRC (0x01)
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#define CLK_PLL_SRC (0x02)
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#define PRE_DIV_SRC (0x03)
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/* */
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#define TCON_PLL_VIDEO_X1 (0x000)
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#define TCON_PLL_VIDEO_X2 (0x002)
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#define PLL_CPU_ENABLE_STATE (0x1<<31)
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#define PLL_CPU_HAS_BEEN_STABLE (0x1<<28)
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#define PLL_CPU_DIV_P(reg) ((reg>>16)&0x3)
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#define PLL_CPU_FACTOR_N(reg) ((reg>>8)&0x1f)
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#define PLL_CPU_FACTOR_K(reg) ((reg>>4)&0x3)
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#define PLL_CPU_FACTOR_M(reg) ((reg)&0x3)
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#define PLL_AUDIO_ENABLE_STATE (0x1<<31)
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#define PLL_AUDIO_HAS_BEEN_STABLE (0x1<<28)
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#define PLL_AUDIO_FACTOR_N(reg) ((reg>>8)&0x7f)
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#define PLL_AUDIO_PREDIV_M(reg) ((reg)&0x1f)
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#define PLL_VIDEO_ENABLE_STATE (0x1<<31)
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#define PLL_VIDEO_MODE (0x1<<30)
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#define PLL_VIDEO_HAS_BEEN_STABLE (0x1<<28)
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#define PLL_VIDEO_FRAC_CLK_OUT (0x1<<25)
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#define PLL_VIDEO_MODE_SEL (0x1<<24)
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#define PLL_VIDEO_SDM_EN (0x1<<20)
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#define PLL_VIDEO_FACTOR_N(reg) ((reg>>8)&0x7f)
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#define PLL_VIDEO_PREDIV_M(reg) (reg&0xf)
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#define PLL_VE_ENABLE_STATE (0x1<<31)
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#define PLL_VE_HAS_BEEN_STABLE (0x1<<28)
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#define PLL_VE_FRAC_CLK_OUT (0x1<<25)
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#define PLL_VE_MODE_SEL (0x1<<24)
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#define PLL_VE_FACTOR_N(reg) ((reg>>8)&0x7f)
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#define PLL_VE_PREDIV_M(reg) (reg&0xf)
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#define PLL_DDR_ENABLE_STATE (0x1<<31)
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#define PLL_DDR_HAS_BEEN_STABLE (0x1<<28)
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#define SDRAM_SIGMA_DELTA_EN (0x1<<24)
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#define PLL_DDR_CFG_UPDATE (0x1<<20)
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#define PLL_DDR_FACTOR_N(reg) ((reg>>8)&0x1f)
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#define PLL_DDR_FACTOR_K(reg) ((reg>>4)&0x3)
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#define PLL_DDR_FACTOR_M(reg) ((reg)&0x3)
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#define PLL_PERIPH_ENABLE_STATE (0x1<<31)
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#define PLL_PERIPH_HAS_BEEN_STABLE (0x1<<28)
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#define PLL_PERIPH_24M_OUT_EN (0x1<<18)
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#define PLL_PERIPH_24M_POST_DIV(reg) ((reg>>16)&0x3)
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#define PLL_PERIPH_FACTOR_N(reg) ((reg>>8)&0x1f)
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#define PLL_PERIPH_FACTOR_K(reg) ((reg>>4)&0x3)
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#define PLL_PERIPH_FACTOR_M(reg) (reg&0x3)
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#define HCLKC_DIV(reg) ((reg>>16)&0x3)
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#define AHB_SRC_SEL(reg) ((reg>>12)&0x3)
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#define AHB_CLK_DIV(reg) ((reg>>4)&0x3)
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#define AHB_PRE_DIV(reg) ((reg>>6)&0x3)
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#define APH_CLK_PATIO(reg) ((reg>>8)&0x3)
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#define CCM_MMC_CTRL_OSCM24 (0x00)
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#define CCM_MMC_CTRL_PLL_PERIPH (0x01)
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#define CCU_BASE_ADDR (0x01C20000)
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#define _24MHZ_ (24000000U)
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#define _32KHZ_ (32000U)
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/* GATE */
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#define BUS_GATE_OFFSET_BIT (12)
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enum bus_gate
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{
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USB_OTG_GATING = (0x18 | (0x0 << BUS_GATE_OFFSET_BIT)),
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SPI1_GATING = (0x15 | (0x0 << BUS_GATE_OFFSET_BIT)),
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SPI0_GATING = (0x14 | (0x0 << BUS_GATE_OFFSET_BIT)),
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SDRAM_GATING = (0x0E | (0x0 << BUS_GATE_OFFSET_BIT)),
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SD1_GATING = (0x09 | (0x0 << BUS_GATE_OFFSET_BIT)),
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SD0_GATING = (0x08 | (0x0 << BUS_GATE_OFFSET_BIT)),
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DMA_GATING = (0x06 | (0x0 << BUS_GATE_OFFSET_BIT)),
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DEFE_GATING = (0x0E | (0x1 << BUS_GATE_OFFSET_BIT)),
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DEBE_GATING = (0x0C | (0x1 << BUS_GATE_OFFSET_BIT)),
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TVE_GATING = (0x0A | (0x1 << BUS_GATE_OFFSET_BIT)),
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TVD_GATING = (0x09 | (0x1 << BUS_GATE_OFFSET_BIT)),
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CSI_GATING = (0x08 | (0x1 << BUS_GATE_OFFSET_BIT)),
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DEINTERLACE_GATING = (0x05 | (0x1 << BUS_GATE_OFFSET_BIT)),
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LCD_GATING = (0x04 | (0x1 << BUS_GATE_OFFSET_BIT)),
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VE_GATING = (0x00 | (0x1 << BUS_GATE_OFFSET_BIT)),
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UART2_GATING = (0x16 | (0x2 << BUS_GATE_OFFSET_BIT)),
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UART1_GATING = (0x15 | (0x2 << BUS_GATE_OFFSET_BIT)),
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UART0_GATING = (0x14 | (0x2 << BUS_GATE_OFFSET_BIT)),
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TWI2_GATING = (0x12 | (0x2 << BUS_GATE_OFFSET_BIT)),
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TWI1_GATING = (0x11 | (0x2 << BUS_GATE_OFFSET_BIT)),
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TWI0_GATING = (0x10 | (0x2 << BUS_GATE_OFFSET_BIT)),
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DAUDIO_GATING = (0x0C | (0x2 << BUS_GATE_OFFSET_BIT)),
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RSB_GATING = (0x03 | (0x2 << BUS_GATE_OFFSET_BIT)),
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CIR_GATING = (0x02 | (0x2 << BUS_GATE_OFFSET_BIT)),
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OWA_GATING = (0x01 | (0x2 << BUS_GATE_OFFSET_BIT)),
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AUDIO_CODEC_GATING = (0x00 | (0x2 << BUS_GATE_OFFSET_BIT)),
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};
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enum dram_gate
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{
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BE_GATING_DRAM = 26,
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FE_GATING_DRAM = 24,
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TVD_GATING_DRAM = 3,
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DEINTERLACE_GATING_DRAM = 2,
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CSI_GATING_DRAM = 1,
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VE_GATING_DRAM = 0
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};
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enum mmc_clk_id
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{
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SDMMC0,
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SDMMC1,
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};
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struct tina_ccu
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{
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volatile rt_uint32_t pll_cpu_ctrl; /* 0x000 */
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volatile rt_uint32_t reserved0;
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volatile rt_uint32_t pll_audio_ctrl; /* 0x008 */
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volatile rt_uint32_t reserved1;
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volatile rt_uint32_t pll_video_ctrl; /* 0x010 */
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volatile rt_uint32_t reserved2;
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volatile rt_uint32_t pll_ve_ctrl; /* 0x018 */
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volatile rt_uint32_t reserved3;
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volatile rt_uint32_t pll_ddr_ctrl; /* 0x020 */
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volatile rt_uint32_t reserved4;
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volatile rt_uint32_t pll_periph_ctrl; /* 0x028 */
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volatile rt_uint32_t reserved5[9];
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volatile rt_uint32_t cpu_clk_src; /* 0x050 */
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volatile rt_uint32_t ahb_apb_hclkc_cfg; /* 0x054 */
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volatile rt_uint32_t reserved6[2];
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volatile rt_uint32_t bus_clk_gating0; /* 0x060 */
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volatile rt_uint32_t bus_clk_gating1; /* 0x064 */
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volatile rt_uint32_t bus_clk_gating2; /* 0x068 */
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volatile rt_uint32_t reserved7[7];
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volatile rt_uint32_t sdmmc0_clk; /* 0x088 */
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volatile rt_uint32_t sdmmc1_clk; /* 0x08C */
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volatile rt_uint32_t reserved8[8];
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volatile rt_uint32_t daudio_clk; /* 0x0B0 */
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volatile rt_uint32_t owa_clk; /* 0x0B4 */
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volatile rt_uint32_t cir_clk; /* 0x0B8 */
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volatile rt_uint32_t reserved9[4];
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volatile rt_uint32_t usbphy_clk; /* 0x0CC */
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volatile rt_uint32_t reserved10[12];
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volatile rt_uint32_t dram_gating; /* 0x100 */
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volatile rt_uint32_t be_clk; /* 0x104 */
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volatile rt_uint32_t reserved11;
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volatile rt_uint32_t fe_clk; /* 0x10C */
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volatile rt_uint32_t reserved12[2];
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volatile rt_uint32_t tcon_clk; /* 0x118*/
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volatile rt_uint32_t di_clk; /* 0x11C */
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volatile rt_uint32_t tve_clk; /* 0x120 */
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volatile rt_uint32_t tvd_clk; /* 0x124 */
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volatile rt_uint32_t reserved13[3];
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volatile rt_uint32_t csi_clk; /* 0x134 */
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volatile rt_uint32_t reserved14;
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volatile rt_uint32_t ve_clk; /* 0x13C */
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volatile rt_uint32_t audio_codec_clk; /* 0x140 */
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volatile rt_uint32_t avs_clk; /* 0x144 */
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volatile rt_uint32_t reserved15[46];
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volatile rt_uint32_t pll_stable_time0; /* 0x200 */
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volatile rt_uint32_t pll_stable_time1; /* 0x204 */
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volatile rt_uint32_t reserved16[6];
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volatile rt_uint32_t pll_cpu_bias; /* 0x220 */
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volatile rt_uint32_t pll_audio_bias; /* 0x224 */
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volatile rt_uint32_t pll_video_bias; /* 0x228 */
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volatile rt_uint32_t pll_ve_bias; /* 0x22C */
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volatile rt_uint32_t pll_ddr_bias; /* 0x230 */
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volatile rt_uint32_t pll_periph_bias; /* 0x234 */
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volatile rt_uint32_t reserved17[6];
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volatile rt_uint32_t pll_cpu_tun; /* 0x250 */
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volatile rt_uint32_t reserved18[3];
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volatile rt_uint32_t pll_ddr_tun; /* 0x260 */
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volatile rt_uint32_t reserved19[8];
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volatile rt_uint32_t pll_audio_pat_ctrl; /* 0x284 */
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volatile rt_uint32_t pll_video_pat_ctrl; /* 0x288 */
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volatile rt_uint32_t reserved20;
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volatile rt_uint32_t pll_ddr_pat_ctrl; /* 0x290 */
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volatile rt_uint32_t reserved21[11];
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volatile rt_uint32_t bus_soft_rst0; /* 0x2C0 */
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volatile rt_uint32_t bus_soft_rst1; /* 0x2C4 */
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volatile rt_uint32_t reserved22[2];
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volatile rt_uint32_t bus_soft_rst2; /* 0x2D0 */
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};
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typedef struct tina_ccu *tina_ccu_t;
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#define CCU ((tina_ccu_t) CCU_BASE_ADDR)
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int cpu_get_pll_clk(void);
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int audio_get_pll_clk(void);
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int video_get_pll_clk(void);
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int ve_get_pll_clk(void);
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int ddr_get_pll_clk(void);
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int periph_get_pll_clk(void);
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int cpu_get_clk(void);
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int ahb_get_clk(void);
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int apb_get_clk(void);
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rt_err_t cpu_set_pll_clk(int clk);
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rt_err_t audio_set_pll_clk(int clk);
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rt_err_t video_set_pll_clk(int clk);
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rt_err_t ve_set_pll_clk(int clk);
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rt_err_t periph_set_pll_clk(int clk);
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rt_err_t cpu_set_clk(int clk);
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rt_err_t bus_gate_clk_enalbe(enum bus_gate bus);
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rt_err_t bus_gate_clk_disalbe(enum bus_gate bus);
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rt_err_t bus_software_reset_enalbe(enum bus_gate bus);
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rt_err_t bus_software_reset_disalbe(enum bus_gate bus);
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rt_err_t dram_gate_clk_enable(enum dram_gate dram_gate);
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rt_err_t dram_gate_clk_disable(enum dram_gate dram_gate);
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rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz);
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#endif |