d724eed9fc
* [kernel][mem] Multiple instances of small memory allocation algorithm * [kernel][mem] Change small memory management algorithm memory header flag * [kernel][mem] Fix assertion problem * [kernel][slab] Multiple instances of slab memory management algorithm * [kernel][memheap] Remove rt_malloc/rt_free/rt_realloc and other related memory interfaces * [kernel][mem] Clean up memory space of small memory management objects * [kernel][kservice] Add memory application interface and thread protection interface * [kernel][kservice] Fix function return value problem * [kernel][memheap] Optimize memheaptrace print * [kernel][memheap] Support best mode * [kernel][memory] Remove semaphore lock * [kernel][memheap] Add locked flag * [kernel][memory] Support malloc memory in interrupt * [kernel][memheap] Add 'memheapcheck' cmd * [kernel][mem] Fix failure to request full memory * [kernel][memheap] Fix compilation warning * [kernel][mem] Fix mem realloc ASSERT * [examples][testcases] Add small mem testcase * [examples][mem_tc] Modify test memory size * [examples][testcases] Add slab memory management algorithm test case * [examples][testcases] fix small memory management algorithm test case * [kernel][memory] Adjusting memory allocation algorithm object definition and interface * [kernel][memory] Fix compilation warning * [examples][utest] Fix mem test case * [examples][utest] fix slab test case * [utest][testcases] Shorten test time * [kernel][memory] Formatting code * [examples][utest] Adjust test run time * [examples][utest] Formatting code * [bsp] update all rtconfig.h |
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README.md
STM32F446-Nucleo BSP Introduction
MCU: STM32F446ZE @180MHz, 512KB FLASH, 128KB RAM
The STM32F446xC/E devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex-M4 core features a floating point unit (FPU) single precision supporting all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security.
The STM32F446xC/E devices incorporate high-speed embedded memories (Flash memory up to 512 Kbytes, up to 128 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. They also feature standard and advanced communication interfaces.
KEY FEATURES
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Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
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Memories
- 512 Kbytes of Flash memory
- 128 Kbytes of SRAM
- Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash memories
- Dual mode QuadSPI interface
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LCD parallel interface, 8080/6800 modes
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Clock, reset and supply management
- 1.7 V to 3.6 V application supply and I/Os
- POR, PDR, PVD and BOR
- 4 to 26 MHz crystal oscillator
- Internal 16 MHz factory-trimmed RC (1% accuracy)
- 32 kHz oscillator for RTC with calibration
- Internal 32 kHz RC with calibration
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Low power
- Sleep, Stop and Standby modes
- VBAT supply for RTC, 20×32 bit backup registers plus optional 4 KB backup SRAM
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3× 12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode
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2× 12-bit D/A converters
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General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
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Up to 17 timers: 2x watchdog, 1x SysTick timer and up to twelve 16-bit and two 32-bit timers up to 180 MHz, each with up to four IC/OC/PWM or pulse counter
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Debug mode
- SWD and JTAG interfaces
- Cortex®-M4 Trace Macrocell™
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Up to 114 I/O ports with interrupt capability
- Up to 111 fast I/Os up to 90 MHz
- Up to 112 5 V-tolerant I/Os
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Up to 20 communication interfaces
- SPDIF-Rx
- Up to 4× I2C interfaces (SMBus/PMBus)
- Up to four USARTs and two UARTs (11.25 Mbit/s, ISO7816 interface, LIN, IrDA, modem control)
- Up to four SPIs (45 Mbits/s), three with muxed I2S for audio class accuracy via internal audio PLL or external clock
- 2x SAI (serial audio interface)
- 2× CAN (2.0B Active)
- SDIO interface
- Consumer electronics control (CEC) I/F
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Advanced connectivity
- USB 2.0 full-speed device/host/OTG controller with on-chip PHY
- USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI
- Dedicated USB power rail enabling on-chip PHYs operation throughout the entire MCU power supply range
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8- to 14-bit parallel camera interface up to 54 Mbytes/s
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CRC calculation unit
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RTC: subsecond accuracy, hardware calendar
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96-bit unique ID
Read more
| Documents | Description |
|---|---|
| STM32_Nucleo-144_BSP_Introduction | How to run RT-Thread on STM32 Nucleo-144 boards (Must-Read) |
| STM32F446ZE ST Official Website | STM32F446ZE datasheet and other resources |
Maintained By
Translated By
Meco Man @ RT-Thread Community