139 lines
4.8 KiB
C
139 lines
4.8 KiB
C
/*
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* The Clear BSD License
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_pit.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.pit"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the instance from the base address to be used to gate or ungate the module clock
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*
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* @param base PIT peripheral base address
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*
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* @return The PIT instance
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*/
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static uint32_t PIT_GetInstance(PIT_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to PIT bases for each instance. */
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static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to PIT clocks for each instance. */
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static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t PIT_GetInstance(PIT_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_pitBases); instance++)
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{
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if (s_pitBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_pitBases));
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return instance;
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}
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void PIT_Init(PIT_Type *base, const pit_config_t *config)
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{
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assert(config);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate the PIT clock*/
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CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS
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/* Enable PIT timers */
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base->MCR &= ~PIT_MCR_MDIS_MASK;
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#endif
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/* Config timer operation when in debug mode */
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if (config->enableRunInDebug)
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{
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base->MCR &= ~PIT_MCR_FRZ_MASK;
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}
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else
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{
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base->MCR |= PIT_MCR_FRZ_MASK;
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}
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}
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void PIT_Deinit(PIT_Type *base)
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{
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#if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS
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/* Disable PIT timers */
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base->MCR |= PIT_MCR_MDIS_MASK;
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#endif
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Gate the PIT clock*/
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CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
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uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base)
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{
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uint32_t valueH = 0U;
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uint32_t valueL = 0U;
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/* LTMR64H should be read before LTMR64L */
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valueH = base->LTMR64H;
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valueL = base->LTMR64L;
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return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
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}
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#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */
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