110 lines
4.2 KiB
Plaintext
110 lines
4.2 KiB
Plaintext
#! armcc -E
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/*
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** ###################################################################
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** Processors: MIMXRT1021CAF4A
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** MIMXRT1021CAG4A
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** MIMXRT1021DAF5A
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** MIMXRT1021DAG5A
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**
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** Compiler: Keil ARM C/C++ Compiler
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** Reference manual: IMXRT1020RM Rev. C, 02/2018
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** Version: rev. 0.1, 2017-06-06
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** Build: b180316
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**
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** Abstract:
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** Linker file for the Keil ARM C/C++ Compiler
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**
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** The Clear BSD License
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2018 NXP
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** All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without
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** modification, are permitted (subject to the limitations in the
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** disclaimer below) provided that the following conditions are met:
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**
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** * Redistributions of source code must retain the above copyright
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** notice, this list of conditions and the following disclaimer.
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**
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** * Redistributions in binary form must reproduce the above copyright
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** notice, this list of conditions and the following disclaimer in the
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** documentation and/or other materials provided with the distribution.
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**
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** * Neither the name of the copyright holder nor the names of its
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** contributors may be used to endorse or promote products derived from
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** this software without specific prior written permission.
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**
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** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
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** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** ###################################################################
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*/
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#define m_interrupts_start 0x00000000
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#define m_interrupts_size 0x00000400
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#define m_text_start 0x00000400
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#define m_text_size 0x0000FC00
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#define m_data_start 0x80000000
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#define m_data_size 0x01E00000
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#define m_ncache_start 0x81E00000
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#define m_ncache_size 0x00200000
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#define m_data2_start 0x20000000
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#define m_data2_size 0x00010000
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#define m_data3_start 0x20200000
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#define m_data3_size 0x00020000
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/* Sizes */
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#if (defined(__stack_size__))
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#define Stack_Size __stack_size__
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#else
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#define Stack_Size 0x0400
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#endif
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#if (defined(__heap_size__))
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#define Heap_Size __heap_size__
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#else
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#define Heap_Size 0x0400
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#endif
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LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size { ; load region size_region
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VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
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* (RESET,+FIRST)
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}
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ER_m_text m_text_start m_text_size { ; load address = execution address
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* (InRoot$$Sections)
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.ANY (+RO)
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}
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RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
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.ANY (+RW +ZI)
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*(m_usb_dma_init_data)
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*(m_usb_dma_noninit_data)
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}
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ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
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}
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ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
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}
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RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
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* (NonCacheable.init)
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* (NonCacheable)
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}
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}
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