751 lines
22 KiB
C
751 lines
22 KiB
C
/**
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* \file
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*
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* \brief SAM I2S - Inter-IC Sound Controller
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*
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* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#include "i2s.h"
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/**
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* \brief Initializes a hardware I<SUP>2</SUP>S module instance
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*
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* Enables the clock and initialize the I<SUP>2</SUP>S module.
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*
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* \param[in,out] module_inst Pointer to the software module instance struct
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* \param[in] hw Pointer to the TCC hardware module
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*
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* \return Status of the initialization procedure.
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*
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* \retval STATUS_OK The module was initialized successfully
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* \retval STATUS_BUSY Hardware module was busy when the
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* initialization procedure was attempted
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* \retval STATUS_ERR_DENIED Hardware module was already enabled
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*/
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enum status_code i2s_init(
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struct i2s_module *const module_inst,
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I2s *hw)
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{
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Assert(module_inst);
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Assert(hw);
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/* Enable the user interface clock in the PM */
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system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_I2S);
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/* Status check */
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uint32_t ctrla;
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ctrla = module_inst->hw->CTRLA.reg;
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if (ctrla & I2S_CTRLA_ENABLE) {
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if (ctrla & (I2S_CTRLA_SEREN1 |
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I2S_CTRLA_SEREN0 | I2S_CTRLA_CKEN1 | I2S_CTRLA_CKEN0)) {
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return STATUS_BUSY;
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} else {
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return STATUS_ERR_DENIED;
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}
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}
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/* Initialize module */
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module_inst->hw = hw;
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/* Initialize serializers */
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#if I2S_CALLBACK_MODE == true
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int i, j;
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for (i = 0; i < 2; i ++) {
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for (j = 0; j < I2S_SERIALIZER_CALLBACK_N; j ++) {
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module_inst->serializer[i].callback[j] = NULL;
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}
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module_inst->serializer[i].registered_callback_mask = 0;
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module_inst->serializer[i].enabled_callback_mask = 0;
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module_inst->serializer[i].job_buffer = NULL;
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module_inst->serializer[i].job_status = STATUS_OK;
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module_inst->serializer[i].requested_words = 0;
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module_inst->serializer[i].transferred_words = 0;
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module_inst->serializer[i].mode = I2S_SERIALIZER_RECEIVE;
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module_inst->serializer[i].data_size = I2S_DATA_SIZE_32BIT;
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}
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_i2s_instances[0] = module_inst;
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system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_I2S);
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#endif
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return STATUS_OK;
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}
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/**
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* \brief Configure specified I<SUP>2</SUP>S clock unit
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*
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* Enables the clock and initialize the clock unit, based on the given
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* configurations.
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*
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* \param[in,out] module_inst Pointer to the software module instance struct
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* \param[in] clock_unit I<SUP>2</SUP>S clock unit to initialize and configure
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* \param[in] config Pointer to the I<SUP>2</SUP>S clock unit configuration
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* options struct
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*
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* \return Status of the configuration procedure.
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*
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* \retval STATUS_OK The module was initialized successfully
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* \retval STATUS_BUSY Hardware module was busy when the
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* configuration procedure was attempted
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* \retval STATUS_ERR_DENIED Hardware module was already enabled
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* \retval STATUS_ERR_INVALID_ARG Invalid divider value or
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* MCK direction setting conflict
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*/
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enum status_code i2s_clock_unit_set_config(
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struct i2s_module *const module_inst,
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const enum i2s_clock_unit clock_unit,
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const struct i2s_clock_unit_config *config)
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{
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Assert(module_inst);
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Assert(module_inst->hw);
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Assert(clock_unit < I2S_CLOCK_UNIT_N);
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Assert(config);
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/* Status check */
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uint32_t ctrla, syncbusy;
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syncbusy = module_inst->hw->SYNCBUSY.reg;
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ctrla = module_inst->hw->CTRLA.reg;
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/* Busy ? */
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if (syncbusy & (I2S_SYNCBUSY_CKEN0 << clock_unit)) {
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return STATUS_BUSY;
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}
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/* Already enabled ? */
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if (ctrla & (I2S_CTRLA_CKEN0 << clock_unit)) {
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return STATUS_ERR_DENIED;
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}
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/* Parameter check */
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if (config->clock.mck_src && config->clock.mck_out_enable) {
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return STATUS_ERR_INVALID_ARG;
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}
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/* Initialize Clock Unit */
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uint32_t clkctrl =
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(config->clock.mck_out_invert ? I2S_CLKCTRL_MCKOUTINV : 0) |
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(config->clock.sck_out_invert ? I2S_CLKCTRL_SCKOUTINV : 0) |
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(config->frame.frame_sync.invert_out ? I2S_CLKCTRL_FSOUTINV : 0) |
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(config->clock.mck_out_enable ? I2S_CLKCTRL_MCKEN : 0) |
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(config->clock.mck_src ? I2S_CLKCTRL_MCKSEL : 0) |
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(config->clock.sck_src ? I2S_CLKCTRL_SCKSEL : 0) |
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(config->frame.frame_sync.invert_use ? I2S_CLKCTRL_FSINV : 0) |
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(config->frame.frame_sync.source ? I2S_CLKCTRL_FSSEL : 0) |
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(config->frame.data_delay ? I2S_CLKCTRL_BITDELAY : 0);
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uint8_t div_val = config->clock.mck_out_div;
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if ((div_val > 0x21) || (div_val == 0)) {
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return STATUS_ERR_INVALID_ARG;
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} else {
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div_val --;
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}
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clkctrl |= I2S_CLKCTRL_MCKOUTDIV(div_val);
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div_val = config->clock.sck_div;
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if ((div_val > 0x21) || (div_val == 0)) {
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return STATUS_ERR_INVALID_ARG;
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} else {
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div_val --;
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}
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clkctrl |= I2S_CLKCTRL_MCKDIV(div_val);
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uint8_t number_slots = config->frame.number_slots;
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if (number_slots > 8) {
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return STATUS_ERR_INVALID_ARG;
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} else if (number_slots > 0) {
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number_slots --;
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}
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clkctrl |=
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I2S_CLKCTRL_NBSLOTS(number_slots) |
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I2S_CLKCTRL_FSWIDTH(config->frame.frame_sync.width) |
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I2S_CLKCTRL_SLOTSIZE(config->frame.slot_size);
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/* Write clock unit configurations */
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module_inst->hw->CLKCTRL[clock_unit].reg = clkctrl;
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/* Select general clock source */
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const uint8_t i2s_gclk_ids[2] = {I2S_GCLK_ID_0, I2S_GCLK_ID_1};
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struct system_gclk_chan_config gclk_chan_config;
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system_gclk_chan_get_config_defaults(&gclk_chan_config);
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gclk_chan_config.source_generator = config->clock.gclk_src;
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system_gclk_chan_set_config(i2s_gclk_ids[clock_unit], &gclk_chan_config);
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system_gclk_chan_enable(i2s_gclk_ids[clock_unit]);
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/* Initialize pins */
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struct system_pinmux_config pin_config;
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system_pinmux_get_config_defaults(&pin_config);
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if (config->mck_pin.enable) {
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pin_config.mux_position = config->mck_pin.mux;
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system_pinmux_pin_set_config(config->mck_pin.gpio, &pin_config);
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}
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if (config->sck_pin.enable) {
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pin_config.mux_position = config->sck_pin.mux;
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system_pinmux_pin_set_config(config->sck_pin.gpio, &pin_config);
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}
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if (config->fs_pin.enable) {
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pin_config.mux_position = config->fs_pin.mux;
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system_pinmux_pin_set_config(config->fs_pin.gpio, &pin_config);
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}
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return STATUS_OK;
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}
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/**
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* \brief Configure specified I<SUP>2</SUP>S serializer
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*
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* Enables the clock and initialize the serializer, based on the given
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* configurations.
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*
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* \param[in,out] module_inst Pointer to the software module instance struct
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* \param[in] serializer I<SUP>2</SUP>S serializer to initialize and configure
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* \param[in] config Pointer to the I<SUP>2</SUP>S serializer configuration
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* options struct
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*
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* \return Status of the configuration procedure.
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*
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* \retval STATUS_OK The module was initialized successfully
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* \retval STATUS_BUSY Hardware module was busy when the
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* configuration procedure was attempted
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* \retval STATUS_ERR_DENIED Hardware module was already enabled
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*/
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enum status_code i2s_serializer_set_config(
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struct i2s_module *const module_inst,
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const enum i2s_serializer serializer,
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const struct i2s_serializer_config *config)
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{
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Assert(module_inst);
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Assert(module_inst->hw);
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Assert(serializer < I2S_SERIALIZER_N);
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Assert(config);
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/* Status check */
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uint32_t ctrla, syncbusy;
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syncbusy = module_inst->hw->SYNCBUSY.reg;
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ctrla = module_inst->hw->CTRLA.reg;
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/* Busy ? */
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if (syncbusy & ((I2S_SYNCBUSY_SEREN0 | I2S_SYNCBUSY_DATA0) << serializer)) {
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return STATUS_BUSY;
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}
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/* Already enabled ? */
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if (ctrla & (I2S_CTRLA_CKEN0 << serializer)) {
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return STATUS_ERR_DENIED;
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}
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/* Initialize Serializer */
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uint32_t serctrl =
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(config->loop_back ? I2S_SERCTRL_RXLOOP : 0) |
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(config->dma_usage ? I2S_SERCTRL_DMA : 0) |
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(config->mono_mode ? I2S_SERCTRL_MONO : 0) |
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(config->disable_data_slot[7] ? I2S_SERCTRL_SLOTDIS7 : 0) |
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(config->disable_data_slot[6] ? I2S_SERCTRL_SLOTDIS6 : 0) |
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(config->disable_data_slot[5] ? I2S_SERCTRL_SLOTDIS5 : 0) |
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(config->disable_data_slot[4] ? I2S_SERCTRL_SLOTDIS4 : 0) |
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(config->disable_data_slot[3] ? I2S_SERCTRL_SLOTDIS3 : 0) |
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(config->disable_data_slot[2] ? I2S_SERCTRL_SLOTDIS2 : 0) |
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(config->disable_data_slot[1] ? I2S_SERCTRL_SLOTDIS1 : 0) |
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(config->disable_data_slot[0] ? I2S_SERCTRL_SLOTDIS0 : 0) |
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(config->transfer_lsb_first ? I2S_SERCTRL_BITREV : 0) |
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(config->data_adjust_left_in_word ? I2S_SERCTRL_WORDADJ : 0) |
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(config->data_adjust_left_in_slot ? I2S_SERCTRL_SLOTADJ : 0) |
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(config->data_padding ? I2S_SERCTRL_TXSAME : 0);
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if (config->clock_unit < I2S_CLOCK_UNIT_N) {
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serctrl |= (config->clock_unit ? I2S_SERCTRL_CLKSEL : 0);
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} else {
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return STATUS_ERR_INVALID_ARG;
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}
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serctrl |=
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I2S_SERCTRL_SERMODE(config->mode) |
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I2S_SERCTRL_TXDEFAULT(config->line_default_state) |
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I2S_SERCTRL_DATASIZE(config->data_size) |
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I2S_SERCTRL_EXTEND(config->bit_padding);
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/* Write Serializer configuration */
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module_inst->hw->SERCTRL[serializer].reg = serctrl;
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/* Initialize pins */
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struct system_pinmux_config pin_config;
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system_pinmux_get_config_defaults(&pin_config);
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if (config->data_pin.enable) {
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pin_config.mux_position = config->data_pin.mux;
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system_pinmux_pin_set_config(config->data_pin.gpio, &pin_config);
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}
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/* Save configure */
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module_inst->serializer[serializer].mode = config->mode;
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module_inst->serializer[serializer].data_size = config->data_size;
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return STATUS_OK;
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}
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/**
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* \brief Retrieves the current module status.
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*
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* Retrieves the status of the module, giving overall state information.
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*
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* \param[in] module_inst Pointer to the I<SUP>2</SUP>S software instance struct
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*
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* \return Bitmask of \c I2S_STATUS_* flags.
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*
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* \retval I2S_STATUS_SYNC_BUSY Module is busy synchronization
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* \retval I2S_STATUS_TRANSMIT_UNDERRUN(x) Serializer x (0~1) is underrun
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* \retval I2S_STATUS_TRANSMIT_READY(x) Serializer x (0~1) is ready to
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* transmit new data word
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* \retval I2S_STATUS_RECEIVE_OVERRUN(x) Serializer x (0~1) is overrun
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* \retval I2S_STATUS_RECEIVE_READY(x) Serializer x (0~1) has data ready to
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* read
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*/
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uint32_t i2s_get_status(
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const struct i2s_module *const module_inst)
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{
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/* Sanity check arguments */
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Assert(module_inst);
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Assert(module_inst->hw);
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uint32_t intflag = module_inst->hw->INTFLAG.reg;
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uint32_t status;
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if (module_inst->hw->SYNCBUSY.reg) {
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status = I2S_STATUS_SYNC_BUSY;
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} else {
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status = 0;
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}
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if (intflag & I2S_INTFLAG_TXUR0) {
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status |= I2S_STATUS_TRANSMIT_UNDERRUN(0);
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}
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if (intflag & I2S_INTFLAG_TXUR1) {
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status |= I2S_STATUS_TRANSMIT_UNDERRUN(1);
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}
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if ((intflag & I2S_INTFLAG_TXRDY0) &&
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!module_inst->hw->SYNCBUSY.bit.DATA0) {
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status |= I2S_STATUS_TRANSMIT_READY(0);
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}
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if ((intflag & I2S_INTFLAG_TXRDY1) &&
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!module_inst->hw->SYNCBUSY.bit.DATA1) {
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status |= I2S_STATUS_TRANSMIT_READY(1);
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}
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if (intflag & I2S_INTFLAG_RXOR0) {
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status |= I2S_STATUS_RECEIVE_OVERRUN(0);
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}
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if (intflag & I2S_INTFLAG_RXOR1) {
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status |= I2S_STATUS_RECEIVE_OVERRUN(1);
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}
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if (intflag & I2S_INTFLAG_RXRDY0) {
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status |= I2S_STATUS_RECEIVE_READY(0);
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}
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if (intflag & I2S_INTFLAG_RXRDY1) {
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status |= I2S_STATUS_RECEIVE_READY(1);
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}
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return status;
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}
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/**
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* \brief Clears a module status flags.
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*
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* Clears the given status flags of the module.
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*
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* \param[in] module_inst Pointer to the I<SUP>2</SUP>S software instance struct
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* \param[in] status Bitmask of \c I2S_STATUS_* flags to clear
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*/
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void i2s_clear_status(
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const struct i2s_module *const module_inst,
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uint32_t status)
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{
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/* Sanity check arguments */
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Assert(module_inst);
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Assert(module_inst->hw);
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uint32_t intflag = 0;
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if (status & I2S_STATUS_TRANSMIT_UNDERRUN(0)) {
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intflag = I2S_INTFLAG_TXUR0;
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}
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if (status & I2S_STATUS_TRANSMIT_UNDERRUN(1)) {
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intflag = I2S_INTFLAG_TXUR1;
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}
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if (status & I2S_STATUS_TRANSMIT_READY(0)) {
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intflag = I2S_INTFLAG_TXRDY0;
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}
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if (status & I2S_STATUS_TRANSMIT_READY(1)) {
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intflag = I2S_INTFLAG_TXRDY1;
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}
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if (status & I2S_STATUS_RECEIVE_OVERRUN(0)) {
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intflag = I2S_INTFLAG_RXOR0;
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}
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if (status & I2S_STATUS_RECEIVE_OVERRUN(1)) {
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intflag = I2S_INTFLAG_RXOR1;
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}
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if (status & I2S_STATUS_RECEIVE_READY(0)) {
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intflag = I2S_INTFLAG_RXRDY0;
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}
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if (status & I2S_STATUS_RECEIVE_READY(1)) {
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intflag = I2S_INTFLAG_RXRDY1;
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}
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module_inst->hw->INTFLAG.reg = intflag;
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}
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/**
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* \brief Enable interrupts on status set
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*
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* Enable the given status interrupt request from the I<SUP>2</SUP>S module.
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*
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* \param[in] module_inst Pointer to the I<SUP>2</SUP>S software instance struct
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* \param[in] status Status interrupts to enable
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*
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* \return Status of enable procedure.
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*
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* \retval STATUS_OK Interrupt is enabled successfully
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* \retval STATUS_ERR_INVALID_ARG Status with no interrupt is passed
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*/
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enum status_code i2s_enable_status_interrupt(
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struct i2s_module *const module_inst,
|
|
uint32_t status)
|
|
{
|
|
/* Sanity check arguments */
|
|
Assert(module_inst);
|
|
|
|
/* No sync busy interrupt */
|
|
if (status & I2S_STATUS_SYNC_BUSY) {
|
|
return STATUS_ERR_INVALID_ARG;
|
|
}
|
|
Assert(module_inst->hw);
|
|
|
|
uint32_t intflag = 0;
|
|
if (status & I2S_STATUS_TRANSMIT_UNDERRUN(0)) {
|
|
intflag = I2S_INTFLAG_TXUR0;
|
|
}
|
|
if (status & I2S_STATUS_TRANSMIT_UNDERRUN(1)) {
|
|
intflag = I2S_INTFLAG_TXUR1;
|
|
}
|
|
if (status & I2S_STATUS_TRANSMIT_READY(0)) {
|
|
intflag = I2S_INTFLAG_TXRDY0;
|
|
}
|
|
if (status & I2S_STATUS_TRANSMIT_READY(1)) {
|
|
intflag = I2S_INTFLAG_TXRDY1;
|
|
}
|
|
if (status & I2S_STATUS_RECEIVE_OVERRUN(0)) {
|
|
intflag = I2S_INTFLAG_RXOR0;
|
|
}
|
|
if (status & I2S_STATUS_RECEIVE_OVERRUN(1)) {
|
|
intflag = I2S_INTFLAG_RXOR1;
|
|
}
|
|
if (status & I2S_STATUS_RECEIVE_READY(0)) {
|
|
intflag = I2S_INTFLAG_RXRDY0;
|
|
}
|
|
if (status & I2S_STATUS_RECEIVE_READY(1)) {
|
|
intflag = I2S_INTFLAG_RXRDY1;
|
|
}
|
|
module_inst->hw->INTENSET.reg = intflag;
|
|
return STATUS_OK;
|
|
}
|
|
|
|
/**
|
|
* \brief Disable interrupts on status set
|
|
*
|
|
* Disable the given status interrupt request from the I<SUP>2</SUP>S module.
|
|
*
|
|
* \param[in] module_inst Pointer to the I<SUP>2</SUP>S software instance struct
|
|
* \param[in] status Status interrupts to disable
|
|
*/
|
|
void i2s_disable_status_interrupt(
|
|
struct i2s_module *const module_inst,
|
|
uint32_t status)
|
|
{
|
|
/* Sanity check arguments */
|
|
Assert(module_inst);
|
|
Assert(module_inst->hw);
|
|
|
|
uint32_t intflag = 0;
|
|
if (status & I2S_STATUS_TRANSMIT_UNDERRUN(0)) {
|
|
intflag = I2S_INTFLAG_TXUR0;
|
|
}
|
|
if (status & I2S_STATUS_TRANSMIT_UNDERRUN(1)) {
|
|
intflag = I2S_INTFLAG_TXUR1;
|
|
}
|
|
if (status & I2S_STATUS_TRANSMIT_READY(0)) {
|
|
intflag = I2S_INTFLAG_TXRDY0;
|
|
}
|
|
if (status & I2S_STATUS_TRANSMIT_READY(1)) {
|
|
intflag = I2S_INTFLAG_TXRDY1;
|
|
}
|
|
if (status & I2S_STATUS_RECEIVE_OVERRUN(0)) {
|
|
intflag = I2S_INTFLAG_RXOR0;
|
|
}
|
|
if (status & I2S_STATUS_RECEIVE_OVERRUN(1)) {
|
|
intflag = I2S_INTFLAG_RXOR1;
|
|
}
|
|
if (status & I2S_STATUS_RECEIVE_READY(0)) {
|
|
intflag = I2S_INTFLAG_RXRDY0;
|
|
}
|
|
if (status & I2S_STATUS_RECEIVE_READY(1)) {
|
|
intflag = I2S_INTFLAG_RXRDY1;
|
|
}
|
|
module_inst->hw->INTENCLR.reg = intflag;
|
|
}
|
|
|
|
|
|
/**
|
|
* \brief Write buffer to the specified Serializer of I<SUP>2</SUP>S module
|
|
*
|
|
* \param[in] module_inst Pointer to the software module instance struct
|
|
* \param[in] serializer The serializer to write to
|
|
* \param[in] buffer The data buffer to write
|
|
* \param[in] size Number of data words to write
|
|
*
|
|
* \return Status of the initialization procedure.
|
|
*
|
|
* \retval STATUS_OK The data was sent successfully
|
|
* \retval STATUS_ERR_DENIED The module or serializer is disabled
|
|
* \retval STATUS_ERR_INVALID_ARG An invalid buffer pointer was supplied
|
|
*/
|
|
enum status_code i2s_serializer_write_buffer_wait(
|
|
const struct i2s_module *const module_inst,
|
|
enum i2s_serializer serializer,
|
|
void *buffer, uint32_t size)
|
|
{
|
|
Assert(module_inst);
|
|
Assert(module_inst->hw);
|
|
Assert(serializer < I2S_SERIALIZER_N);
|
|
Assert(buffer);
|
|
|
|
if (size == 0) {
|
|
return STATUS_OK;
|
|
}
|
|
|
|
uint8_t data_size = 1; /* number of bytes */
|
|
struct i2s_serializer_module *data_module = (struct i2s_serializer_module *)
|
|
&module_inst->serializer[serializer];
|
|
|
|
/* Check buffer */
|
|
switch(data_module->data_size) {
|
|
case I2S_DATA_SIZE_32BIT:
|
|
case I2S_DATA_SIZE_24BIT:
|
|
case I2S_DATA_SIZE_20BIT:
|
|
case I2S_DATA_SIZE_18BIT:
|
|
if ((uint32_t)buffer & 0x3) {
|
|
return STATUS_ERR_INVALID_ARG;
|
|
}
|
|
data_size = 4;
|
|
break;
|
|
case I2S_DATA_SIZE_16BIT:
|
|
case I2S_DATA_SIZE_16BIT_COMPACT:
|
|
if ((uint32_t)buffer & 0x1) {
|
|
return STATUS_ERR_INVALID_ARG;
|
|
}
|
|
data_size = 2;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Check status */
|
|
if (!(module_inst->hw->CTRLA.reg &
|
|
(I2S_CTRLA_ENABLE | (I2S_CTRLA_SEREN0 << serializer)))) {
|
|
return STATUS_ERR_DENIED;
|
|
}
|
|
|
|
/* Write */
|
|
uint32_t i;
|
|
uint32_t sync_bit = I2S_SYNCBUSY_DATA0 << serializer;
|
|
uint32_t ready_bit = I2S_INTFLAG_TXRDY0 << serializer;
|
|
if (4 == data_size) {
|
|
uint32_t *p32 = (uint32_t*)buffer;
|
|
for (i = 0; i < size; i ++) {
|
|
while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
|
|
/* Wait Tx ready */
|
|
}
|
|
while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
|
|
/* Wait Sync */
|
|
}
|
|
module_inst->hw->DATA[serializer].reg = p32[i];
|
|
module_inst->hw->INTFLAG.reg = ready_bit;
|
|
}
|
|
} else if (2 == data_size) {
|
|
uint16_t *p16 = (uint16_t*)buffer;
|
|
for (i = 0; i < size; i ++) {
|
|
while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
|
|
/* Wait Tx ready */
|
|
}
|
|
while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
|
|
/* Wait Sync */
|
|
}
|
|
module_inst->hw->DATA[serializer].reg = p16[i];
|
|
module_inst->hw->INTFLAG.reg = ready_bit;
|
|
}
|
|
} else {
|
|
uint8_t *p8 = (uint8_t*)buffer;
|
|
for (i = 0; i < size; i ++) {
|
|
while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
|
|
/* Wait Tx ready */
|
|
}
|
|
while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
|
|
/* Wait Sync */
|
|
}
|
|
module_inst->hw->DATA[serializer].reg = p8[i];
|
|
module_inst->hw->INTFLAG.reg = ready_bit;
|
|
}
|
|
}
|
|
|
|
return STATUS_OK;
|
|
}
|
|
|
|
/**
|
|
* \brief Read from the specified Serializer of I<SUP>2</SUP>S module to a buffer
|
|
*
|
|
* \param[in] module_inst Pointer to the software module instance struct
|
|
* \param[in] serializer The serializer to write to
|
|
* \param[in] buffer The buffer to fill read data (NULL to discard)
|
|
* \param[in] size Number of data words to read
|
|
*
|
|
* \return Status of the initialization procedure.
|
|
*
|
|
* \retval STATUS_OK The data was sent successfully
|
|
* \retval STATUS_ERR_DENIED The module or serializer is disabled
|
|
* \retval STATUS_ERR_INVALID_ARG An invalid buffer pointer was supplied
|
|
*/
|
|
enum status_code i2s_serializer_read_buffer_wait(
|
|
const struct i2s_module *const module_inst,
|
|
enum i2s_serializer serializer,
|
|
void *buffer, uint32_t size)
|
|
{
|
|
Assert(module_inst);
|
|
Assert(module_inst->hw);
|
|
|
|
if (size == 0) {
|
|
return STATUS_OK;
|
|
}
|
|
|
|
uint8_t data_size = 1; /* number of bytes */
|
|
struct i2s_serializer_module *data_module = (struct i2s_serializer_module *)
|
|
&module_inst->serializer[serializer];
|
|
|
|
/* Check buffer */
|
|
switch(data_module->data_size) {
|
|
case I2S_DATA_SIZE_32BIT:
|
|
case I2S_DATA_SIZE_24BIT:
|
|
case I2S_DATA_SIZE_20BIT:
|
|
case I2S_DATA_SIZE_18BIT:
|
|
if ((uint32_t)buffer & 0x3) {
|
|
return STATUS_ERR_INVALID_ARG;
|
|
}
|
|
data_size = 4;
|
|
break;
|
|
case I2S_DATA_SIZE_16BIT:
|
|
case I2S_DATA_SIZE_16BIT_COMPACT:
|
|
if ((uint32_t)buffer & 0x1) {
|
|
return STATUS_ERR_INVALID_ARG;
|
|
}
|
|
data_size = 2;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Check status */
|
|
if (!(module_inst->hw->CTRLA.reg &
|
|
(I2S_CTRLA_ENABLE | (I2S_CTRLA_SEREN0 << serializer)))) {
|
|
return STATUS_ERR_DENIED;
|
|
}
|
|
|
|
/* Read */
|
|
uint32_t i;
|
|
uint32_t sync_bit = I2S_SYNCBUSY_DATA0 << serializer;
|
|
uint32_t ready_bit = I2S_INTFLAG_RXRDY0 << serializer;
|
|
if (buffer == NULL) {
|
|
for (i = 0; i < size; i ++) {
|
|
while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
|
|
/* Wait Rx ready */
|
|
}
|
|
while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
|
|
/* Wait Sync */
|
|
}
|
|
module_inst->hw->DATA[serializer].reg;
|
|
module_inst->hw->INTFLAG.reg = ready_bit;
|
|
}
|
|
}
|
|
else if (4 == data_size) {
|
|
uint32_t *p32 = (uint32_t*)buffer;
|
|
for (i = 0; i < size; i ++) {
|
|
while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
|
|
/* Wait Rx ready */
|
|
}
|
|
while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
|
|
/* Wait Sync */
|
|
}
|
|
p32[i] = module_inst->hw->DATA[serializer].reg;
|
|
module_inst->hw->INTFLAG.reg = ready_bit;
|
|
}
|
|
} else if (2 == data_size) {
|
|
uint16_t *p16 = (uint16_t*)buffer;
|
|
for (i = 0; i < size; i ++) {
|
|
while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
|
|
/* Wait Rx ready */
|
|
}
|
|
while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
|
|
/* Wait Sync */
|
|
}
|
|
p16[i] = module_inst->hw->DATA[serializer].reg;
|
|
module_inst->hw->INTFLAG.reg = ready_bit;
|
|
}
|
|
} else {
|
|
uint8_t *p8 = (uint8_t*)buffer;
|
|
for (i = 0; i < size; i ++) {
|
|
while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
|
|
/* Wait Tx ready */
|
|
}
|
|
while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
|
|
/* Wait Sync */
|
|
}
|
|
p8[i] = module_inst->hw->DATA[serializer].reg;
|
|
module_inst->hw->INTFLAG.reg = ready_bit;
|
|
}
|
|
}
|
|
|
|
return STATUS_OK;
|
|
}
|