347 lines
9.8 KiB
C
347 lines
9.8 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-11-11 breo.com first version
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*/
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#include <board.h>
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#include "drv_pwm.h"
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#ifdef RT_USING_PWM
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#if !defined(BSP_USING_TIM1_CH1) && !defined(BSP_USING_TIM1_CH2) && \
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!defined(BSP_USING_TIM1_CH3) && !defined(BSP_USING_TIM1_CH4) && \
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!defined(BSP_USING_TIM2_CH1) && !defined(BSP_USING_TIM2_CH2) && \
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!defined(BSP_USING_TIM2_CH3) && !defined(BSP_USING_TIM2_CH4) && \
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!defined(BSP_USING_TIM3_CH1) && !defined(BSP_USING_TIM3_CH2) && \
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!defined(BSP_USING_TIM3_CH3) && !defined(BSP_USING_TIM3_CH4) && \
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!defined(BSP_USING_TIM4_CH1) && !defined(BSP_USING_TIM4_CH2) && \
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!defined(BSP_USING_TIM4_CH3) && !defined(BSP_USING_TIM4_CH4) && \
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!defined(BSP_USING_TIM5_CH1) && !defined(BSP_USING_TIM5_CH2) && \
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!defined(BSP_USING_TIM5_CH3) && !defined(BSP_USING_TIM5_CH4) && \
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!defined(BSP_USING_TIM8_CH1) && !defined(BSP_USING_TIM8_CH2) && \
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!defined(BSP_USING_TIM8_CH3) && !defined(BSP_USING_TIM8_CH4)
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#error "Please define at least one BSP_USING_TIMx_CHx"
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#endif
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#endif /* RT_USING_PWM */
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#define MAX_PERIOD 65535
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#define MIN_PERIOD 3
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#ifdef BSP_USING_PWM
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struct n32_pwm
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{
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TIM_Module *tim_handle;
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const char *name;
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struct rt_device_pwm pwm_device;
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int8_t tim_en;
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uint8_t ch_en;
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uint32_t period;
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uint32_t psc;
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};
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static struct n32_pwm n32_pwm_obj[] =
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{
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#if defined(BSP_USING_TIM1_CH1) || defined(BSP_USING_TIM1_CH2) || \
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defined(BSP_USING_TIM1_CH3) || defined(BSP_USING_TIM1_CH4)
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{
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.tim_handle = TIM1,
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.name = "tim1pwm",
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},
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#endif
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#if defined(BSP_USING_TIM2_CH1) || defined(BSP_USING_TIM2_CH2) || \
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defined(BSP_USING_TIM2_CH3) || defined(BSP_USING_TIM2_CH4)
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{
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.tim_handle = TIM2,
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.name = "tim2pwm",
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},
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#endif
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#if defined(BSP_USING_TIM3_CH1) || defined(BSP_USING_TIM3_CH2) || \
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defined(BSP_USING_TIM3_CH3) || defined(BSP_USING_TIM3_CH4)
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{
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.tim_handle = TIM3,
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.name = "tim3pwm",
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},
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#endif
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#if defined(BSP_USING_TIM4_CH1) || defined(BSP_USING_TIM4_CH2) || \
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defined(BSP_USING_TIM4_CH3) || defined(BSP_USING_TIM4_CH4)
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{
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.tim_handle = TIM4,
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.name = "tim4pwm",
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},
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#endif
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#if defined(BSP_USING_TIM5_CH1) || defined(BSP_USING_TIM5_CH2) || \
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defined(BSP_USING_TIM5_CH3) || defined(BSP_USING_TIM5_CH4)
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{
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.tim_handle = TIM5,
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.name = "tim5pwm",
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},
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#endif
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#if defined(BSP_USING_TIM8_CH1) || defined(BSP_USING_TIM8_CH2) || \
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defined(BSP_USING_TIM8_CH3) || defined(BSP_USING_TIM8_CH4)
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{
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.tim_handle = TIM8,
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.name = "tim8pwm",
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}
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#endif
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};
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static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
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static struct rt_pwm_ops drv_ops =
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{
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drv_pwm_control
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};
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static rt_err_t drv_pwm_enable(struct n32_pwm *pwm_dev, struct rt_pwm_configuration *configuration, rt_bool_t enable)
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{
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/* Get the value of channel */
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rt_uint32_t channel = configuration->channel;
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TIM_Module *TIMx = pwm_dev->tim_handle;
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if (enable)
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{
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pwm_dev->ch_en |= 0x1 << channel;
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}
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else
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{
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pwm_dev->ch_en &= ~(0x1 << channel);
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}
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if (enable)
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{
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if (channel == 1)
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{
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TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_ENABLE);
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}
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else if (channel == 2)
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{
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TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_ENABLE);
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}
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else if (channel == 3)
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{
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TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_ENABLE);
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}
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else if (channel == 4)
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{
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TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_ENABLE);
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}
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}
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else
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{
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if (channel == 1)
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{
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TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_DISABLE);
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}
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else if (channel == 2)
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{
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TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_DISABLE);
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}
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else if (channel == 3)
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{
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TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_DISABLE);
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}
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else if (channel == 4)
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{
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TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_DISABLE);
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}
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}
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if (pwm_dev->ch_en)
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{
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pwm_dev->tim_en = 0x1;
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TIM_Enable(TIMx, ENABLE);
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}
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else
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{
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pwm_dev->tim_en = 0x0;
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TIM_Enable(TIMx, DISABLE);
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}
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return RT_EOK;
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}
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static rt_err_t drv_pwm_get(struct n32_pwm *pwm_dev, struct rt_pwm_configuration *configuration)
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{
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RCC_ClocksType RCC_Clockstruct;
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rt_uint32_t ar, div, cc1, cc2, cc3, cc4;
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rt_uint64_t tim_clock;
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rt_uint32_t channel = configuration->channel;
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TIM_Module *TIMx = pwm_dev->tim_handle;
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ar = TIMx->AR;
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div = TIMx->PSC;
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cc1 = TIMx->CCDAT1;
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cc2 = TIMx->CCDAT2;
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cc3 = TIMx->CCDAT3;
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cc4 = TIMx->CCDAT4;
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RCC_GetClocksFreqValue(&RCC_Clockstruct);
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tim_clock = RCC_Clockstruct.Pclk2Freq;
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/* Convert nanosecond to frequency and duty cycle. */
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tim_clock /= 1000000UL;
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configuration->period = (ar + 1) * (div + 1) * 1000UL / tim_clock;
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if (channel == 1)
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configuration->pulse = (cc1 + 1) * (div + 1) * 1000UL / tim_clock;
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if (channel == 2)
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configuration->pulse = (cc2 + 1) * (div + 1) * 1000UL / tim_clock;
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if (channel == 3)
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configuration->pulse = (cc3 + 1) * (div + 1) * 1000UL / tim_clock;
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if (channel == 4)
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configuration->pulse = (cc4 + 1) * (div + 1) * 1000UL / tim_clock;
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return RT_EOK;
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}
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static rt_err_t drv_pwm_set(struct n32_pwm *pwm_dev, struct rt_pwm_configuration *configuration)
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{
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TIM_Module *TIMx = pwm_dev->tim_handle;
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rt_uint32_t channel = configuration->channel;
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rt_uint32_t period;
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rt_uint64_t psc;
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rt_uint32_t pulse;
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RCC_ClocksType RCC_Clock;
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RCC_GetClocksFreqValue(&RCC_Clock);
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rt_uint64_t input_clock;
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if ((TIM1 == TIMx) || (TIM8 == TIMx))
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{
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RCC_ConfigTim18Clk(RCC_TIM18CLK_SRC_SYSCLK);
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input_clock = RCC_Clock.SysclkFreq;
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}
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else
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{
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if (1 == (RCC_Clock.HclkFreq / RCC_Clock.Pclk1Freq))
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input_clock = RCC_Clock.Pclk1Freq;
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else
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input_clock = RCC_Clock.Pclk1Freq * 2;
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}
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input_clock /= 1000000UL;
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/* Convert nanosecond to frequency and duty cycle. */
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period = (unsigned long long)configuration->period * input_clock / 1000ULL;
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psc = period / MAX_PERIOD + 1;
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period = period / psc;
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if (period < MIN_PERIOD)
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{
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period = MIN_PERIOD;
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}
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if ((pwm_dev->period != period) || (pwm_dev->psc != psc))
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{
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/* Tim base configuration */
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TIM_TimeBaseInitType TIM_TIMeBaseStructure;
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TIM_InitTimBaseStruct(&TIM_TIMeBaseStructure);
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TIM_TIMeBaseStructure.Period = period - 1;
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TIM_TIMeBaseStructure.Prescaler = psc - 1;
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TIM_TIMeBaseStructure.ClkDiv = 0;
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TIM_TIMeBaseStructure.CntMode = TIM_CNT_MODE_UP;
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TIM_InitTimeBase(TIMx, &TIM_TIMeBaseStructure);
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}
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pulse = (unsigned long long)configuration->pulse * input_clock / psc / 1000ULL;
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if (pulse > period)
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{
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pulse = period;
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}
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/* PWM1 Mode configuration: Channel1 */
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OCInitType TIM_OCInitStructure;
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TIM_InitOcStruct(&TIM_OCInitStructure);
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TIM_OCInitStructure.OcMode = TIM_OCMODE_PWM1;
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TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
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TIM_OCInitStructure.Pulse = pulse;
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TIM_OCInitStructure.OcPolarity = TIM_OC_POLARITY_HIGH;
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if (channel == 1)
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{
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TIM_InitOc1(TIMx, &TIM_OCInitStructure);
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TIM_ConfigOc1Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
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if (!(pwm_dev->ch_en & (0x1 << channel)))
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TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_DISABLE);
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}
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else if (channel == 2)
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{
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TIM_InitOc2(TIMx, &TIM_OCInitStructure);
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TIM_ConfigOc2Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
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if (!(pwm_dev->ch_en & (0x1 << channel)))
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TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_DISABLE);
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}
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else if (channel == 3)
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{
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TIM_InitOc3(TIMx, &TIM_OCInitStructure);
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TIM_ConfigOc3Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
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if (!(pwm_dev->ch_en & (0x1 << channel)))
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TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_DISABLE);
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}
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else if (channel == 4)
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{
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TIM_InitOc4(TIMx, &TIM_OCInitStructure);
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TIM_ConfigOc4Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
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if (!(pwm_dev->ch_en & (0x1 << channel)))
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TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_DISABLE);
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}
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TIM_ConfigArPreload(TIMx, ENABLE);
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TIM_EnableCtrlPwmOutputs(TIMx, ENABLE);
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return RT_EOK;
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}
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static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
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struct n32_pwm *pwm_dev = (struct n32_pwm *)(device->parent.user_data);
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switch (cmd)
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{
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case PWM_CMD_ENABLE:
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return drv_pwm_enable(pwm_dev, configuration, RT_TRUE);
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case PWM_CMD_DISABLE:
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return drv_pwm_enable(pwm_dev, configuration, RT_FALSE);
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case PWM_CMD_SET:
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return drv_pwm_set(pwm_dev, configuration);
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case PWM_CMD_GET:
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return drv_pwm_get(pwm_dev, configuration);
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default:
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return RT_EINVAL;
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}
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}
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static int rt_hw_pwm_init(void)
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{
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int i = 0;
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int result = RT_EOK;
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for (i = 0; i < sizeof(n32_pwm_obj) / sizeof(n32_pwm_obj[0]); i++)
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{
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if (rt_device_pwm_register(&n32_pwm_obj[i].pwm_device,
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n32_pwm_obj[i].name, &drv_ops, &(n32_pwm_obj[i])) == RT_EOK)
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{
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/* Init timer pin and enable clock */
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void n32_msp_tim_init(void *Instance);
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n32_msp_tim_init(n32_pwm_obj[i].tim_handle);
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}
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else
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{
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result = -RT_ERROR;
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}
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}
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_pwm_init);
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#endif
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