158 lines
3.9 KiB
C
158 lines
3.9 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-07-15 Emuzit first version
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*/
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#ifndef __SOC_H__
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#define __SOC_H__
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#include <stdint.h>
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#include <stddef.h>
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#include <assert.h>
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#include <rtdef.h>
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#if !defined(SOC_CH567) && \
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!defined(SOC_CH568) && \
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!defined(SOC_SERIES_CH569)
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#define SOC_SERIES_CH569
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#endif
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#ifndef __packed
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#define __packed __attribute__((packed))
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#endif
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#define CHECK_STRUCT_SIZE(s, size) \
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static_assert(sizeof(s) == size, #s " has wrong size")
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#define BITS_SET(x, bits) do x |= bits; while(0)
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#define BITS_CLR(x, bits) do x &= ~bits; while(0)
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#define FLASH_BASE_ADDRESS 0x00000000
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#define RAMS_BASE_ADDRESS 0x20000000
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#define BUS8_BASE_ADDRESS 0x80000000
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#ifdef SOC_SERIES_CH569
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#define RAMX_BASE_ADDRESS 0x20020000
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#define RAMS_SIZE 16
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#else
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#define RAMS_SIZE 32
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#endif
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#define RAMS_END (RAMS_BASE_ADDRESS + RAMS_SIZE * 1024)
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#define SYS_REG_BASE 0x40001000
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#define GPIO_REG_BASE 0x40001000
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#define GPIO_REG_BASE_PA 0x40001040
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#define GPIO_REG_BASE_PB 0x40001060
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#define GPIO_PORTS 2 // 2 ports : PA & PB
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#define GPIO_PA_PIN_START 0 // PA : pin number 0~31
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#define GPIO_PB_PIN_START 32 // PB : pin number 32~63
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#ifdef SOC_SERIES_CH569
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#define GPIO_PA_PIN_MARK 0x00ffffff // PA : bits 0~23
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#define GPIO_PB_PIN_MARK 0x01ffffff // PB : bits 0~24
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#else
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#define GPIO_PA_PIN_MARK 0x0000ffff // PA : bits 0~15
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#define GPIO_PB_PIN_MARK 0x00003fff // PB : bits 0~13
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#endif
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#define TMR0_REG_BASE 0x40002000
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#define TMR1_REG_BASE 0x40002400
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#define TMR2_REG_BASE 0x40002800
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#define UART0_REG_BASE 0x40003000
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#define UART1_REG_BASE 0x40003400
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#define UART2_REG_BASE 0x40003800
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#define UART3_REG_BASE 0x40003c00
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#define SPI0_REG_BASE 0x40004000
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#define SPI1_REG_BASE 0x40004400
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#define PWMX_REG_BASE 0x40005000
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#define PFIC_REG_BASE 0xe000e000
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#define SysTick_REG_BASE 0xe000f000
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#ifdef SOC_SERIES_CH569
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#define HSPI_REG_BASE 0x40006000 // CH569W
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#define ECDC_REG_BASE 0x40007000
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#define USBSS_REG_BASE 0x40008000
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#define USBHS_REG_BASE 0x40009000
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#define EMMC_REG_BASE 0x4000a000
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#define SERDES_REG_BASE 0x4000b000
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#define ETH_REG_BASE 0x4000c000 // CH565W/CH569W
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#define DVP_REG_BASE 0x4000e000 // CH565W/CH565M
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#else
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#define LED_REG_BASE 0x40006000
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#define USB0_REG_BASE 0x40008000 // CH567
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#define USB1_REG_BASE 0x40009000 // CH567
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#define USB_REG_BASE 0x40009000 // CH568
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#define SDC_REG_BASE 0x4000a000
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#define SATA_REG_BASE 0x4000b000 // CH568
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#define ECDC_REG_BASE 0x4000c400
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#endif
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#if defined(SOC_SERIES_CH569)
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typedef enum
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{
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PWMX_OFFn = 0,
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NMI_IRQn = 2,
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EXC_IRQn = 3,
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SysTick_IRQn = 12,
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SWI_IRQn = 14,
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WDOG_IRQn = 16,
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TMR0_IRQn = 17,
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GPIO_IRQn = 18,
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SPI0_IRQn = 19,
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USBSS_IRQn = 20,
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LINK_IRQn = 21,
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TMR1_IRQn = 22,
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TMR2_IRQn = 23,
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UART0_IRQn = 24,
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USBHS_IRQn = 25,
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EMMC_IRQn = 26,
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DVP_IRQn = 27,
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HSPI_IRQn = 28,
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SPI1_IRQn = 29,
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UART1_IRQn = 30,
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UART2_IRQn = 31,
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UART3_IRQn = 32,
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SerDes_IRQn = 33,
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ETH_IRQn = 34,
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PMT_IRQn = 35,
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ECDC_IRQn = 36,
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END_OF_IRQn
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} irq_number_t;
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#else
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typedef enum
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{
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PWMX_OFFn = 0,
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SOFT_IRQn = 0,
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TMR0_IRQn = 1,
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GPIO_IRQn = 2,
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SPI0_IRQn = 3,
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USB0_IRQn = 4, // CH567
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SATA_IRQn = 4, // CH568
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TMR1_IRQn = 5,
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TMR2_IRQn = 6,
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UART0_IRQn = 7,
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USB1_IRQn = 8,
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SDC_IRQn = 9,
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ECDC_IRQn = 10,
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LED_IRQn = 11,
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SPI1_IRQn = 12,
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UART1_IRQn = 13,
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UART2_IRQn = 14,
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UART3_IRQn = 15,
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END_OF_IRQn
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} irq_number_t;
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#endif
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#endif
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