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https://github.com/RT-Thread/rt-thread.git
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7c66501861
MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
61 lines
1.3 KiB
C
61 lines
1.3 KiB
C
/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-12-04 Jiaxun Yang Initial version
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*/
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#include <rtthread.h>
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#include "mips.h"
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register rt_uint32_t $GP __asm__ ("$28");
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rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
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{
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static rt_uint32_t wSR=0;
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static rt_uint32_t wGP;
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rt_uint8_t *stk;
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struct pt_regs *pt;
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rt_uint32_t i;
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/* Get stack aligned */
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stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
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stk -= sizeof(struct pt_regs);
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pt = (struct pt_regs*)stk;
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for (i = 0; i < 8; ++i)
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{
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pt->pad0[i] = 0xdeadbeef;
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}
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/* Fill Stack register numbers */
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for (i = 0; i < 32; ++i)
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{
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pt->regs[i] = 0xdeadbeef;
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}
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pt->regs[REG_SP] = (rt_uint32_t)stk;
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pt->regs[REG_A0] = (rt_uint32_t)parameter;
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pt->regs[REG_GP] = (rt_uint32_t)$GP;
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pt->regs[REG_FP] = (rt_uint32_t)0x0;
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pt->regs[REG_RA] = (rt_uint32_t)texit;
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pt->hi = 0x0;
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pt->lo = 0x0;
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pt->cp0_status = (ST0_IE | ST0_CU0 | ST0_IM);
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#ifdef RT_USING_FPU
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pt->cp0_status |= (ST0_CU1 | ST0_FR);
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#endif
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pt->cp0_cause = read_c0_cause();
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pt->cp0_epc = (rt_uint32_t)tentry;
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pt->cp0_badvaddr = 0x0;
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return stk;
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}
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