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7c66501861
MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
47 lines
996 B
C
47 lines
996 B
C
/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-12-04 Jiaxun Yang Initial version
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*/
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#ifndef _MIPS_FPU_H_
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#define _MIPS_FPU_H_
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#ifndef __ASSEMBLY__
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#include <mips_regs.h>
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/**
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* init hardware FPU
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*/
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#ifdef RT_USING_FPU
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inline void rt_hw_fpu_init(void)
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{
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rt_uint32_t c0_status = 0;
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rt_uint32_t c1_status = 0;
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/* Enable CU1 */
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c0_status = read_c0_status();
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c0_status |= (ST0_CU1 | ST0_FR);
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write_c0_status(c0_status);
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/* FCSR Configs */
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c1_status = read_c1_status();
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c1_status |= (FPU_CSR_FS | FPU_CSR_FO | FPU_CSR_FN); /* Set FS, FO, FN */
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c1_status &= ~(FPU_CSR_ALL_E); /* Disable exception */
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c1_status = (c1_status & (~FPU_CSR_RM)) | FPU_CSR_RN; /* Set RN */
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write_c1_status(c1_status);
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return ;
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}
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#else
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inline void rt_hw_fpu_init(void){} /* Do nothing */
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#endif
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#endif
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#endif
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