mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2025-01-29 13:00:25 +08:00
7c66501861
MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
60 lines
1.3 KiB
ArmAsm
60 lines
1.3 KiB
ArmAsm
/*
|
|
* Copyright (c) 2006-2019, RT-Thread Development Team
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*
|
|
* Change Logs:
|
|
* Date Author Notes
|
|
* 2019-12-04 Jiaxun Yang Initial version
|
|
*/
|
|
|
|
.section ".exc_vectors", "ax"
|
|
.extern tlb_refill_handler
|
|
.extern cache_error_handler
|
|
.extern mips_irq_handle
|
|
|
|
/* 0x0 - TLB refill handler */
|
|
.global tlb_refill_exception
|
|
.type tlb_refill_exception,@function
|
|
ebase_start:
|
|
tlb_refill_exception:
|
|
b _general_exception_handler
|
|
nop
|
|
|
|
/* 0x100 - Cache error handler */
|
|
.org ebase_start + 0x100
|
|
j cache_error_handler
|
|
nop
|
|
|
|
/* 0x180 - Exception/Interrupt handler */
|
|
.global general_exception
|
|
.type general_exception,@function
|
|
.org ebase_start + 0x180
|
|
general_exception:
|
|
b _general_exception_handler
|
|
nop
|
|
|
|
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
|
|
.global irq_exception
|
|
.type irq_exception,@function
|
|
.org ebase_start + 0x200
|
|
irq_exception:
|
|
b _general_exception_handler
|
|
nop
|
|
|
|
/* general exception handler */
|
|
_general_exception_handler:
|
|
.set noreorder
|
|
la $k0, mips_irq_handle
|
|
jr $k0
|
|
nop
|
|
.set reorder
|
|
|
|
/* interrupt handler */
|
|
_irq_handler:
|
|
.set noreorder
|
|
la $k0, mips_irq_handle
|
|
jr $k0
|
|
nop
|
|
.set reorder
|