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https://github.com/RT-Thread/rt-thread.git
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7c66501861
MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
56 lines
1000 B
ArmAsm
56 lines
1000 B
ArmAsm
/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-12-04 Jiaxun Yang Initial version
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*/
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#ifndef __ASSEMBLY__
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#define __ASSEMBLY__
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#endif
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#include <mips.h>
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#include <rtconfig.h>
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.section ".start", "ax"
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.set noreorder
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/* the program entry */
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.globl _rtthread_entry
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_rtthread_entry:
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#ifndef RT_USING_SELF_BOOT
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.globl _start
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_start:
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#endif
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la ra, _rtthread_entry
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/* disable interrupt */
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mtc0 zero, CP0_CAUSE
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mtc0 zero, CP0_STATUS # Set CPU to disable interrupt.
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ehb
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/* setup stack pointer */
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la sp, _system_stack
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la gp, _gp
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bal rt_cpu_early_init
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nop
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/* clear bss */
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la t0, __bss_start
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la t1, __bss_end
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_clr_bss_loop:
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sw zero, 0(t0)
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bne t0, t1, _clr_bss_loop
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addiu t0, t0, 4
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/* jump to RT-Thread RTOS */
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jal rtthread_startup
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nop
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/* restart, never die */
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j _start
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nop
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