30 lines
591 B
C
30 lines
591 B
C
/*
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* Copyright (c) 2020-2021, WangHuachen
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*
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* SPDX-License-Identifier: MIT
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*
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* Change Logs:
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* Date Author Notes
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* 2020-11-30 WangHuachen the first version
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*/
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#ifndef XIL_CACHE_H
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#define XIL_CACHE_H
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#include <rthw.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define Xil_DCacheFlushRange(addr, size) rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void*)(addr), (size))
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#define Xil_DCacheInvalidateRange(addr, size) rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void*)(addr), (size))
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#ifdef __cplusplus
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}
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#endif
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#endif
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/**
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* @} End of "addtogroup r5_cache_apis".
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*/
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