516 lines
14 KiB
C
516 lines
14 KiB
C
/**
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******************************************************************************
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* @file stm32mp15xx_eval_stpmic1.h
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* @author MCD Application Team
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* @brief stpmu driver functions used for ST internal validation
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*
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******************************************************************************
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*/
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#ifndef __STPMIC_H__
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#define __STPMIC_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "stm32mp1xx_hal.h"
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/* Exported types ------------------------------------------------------------*/
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typedef enum
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{
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STPMU1_BUCK1=1,
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STPMU1_BUCK2,
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STPMU1_BUCK3,
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STPMU1_BUCK4,
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STPMU1_LDO1,
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STPMU1_LDO2,
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STPMU1_LDO3,
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STPMU1_LDO4,
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STPMU1_LDO5,
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STPMU1_LDO6,
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STPMU1_VREFDDR,
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}PMIC_RegulId_TypeDef;
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/* IRQ definitions */
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typedef enum {
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/* Interrupt Register 1 (0x50 for latch) */
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IT_SWOUT_R,
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IT_SWOUT_F,
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IT_VBUS_OTG_R,
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IT_VBUS_OTG_F,
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IT_WAKEUP_R,
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IT_WAKEUP_F,
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IT_PONKEY_R,
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IT_PONKEY_F,
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/* Interrupt Register 2 (0x51 for latch) */
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IT_OVP_BOOST,
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IT_OCP_BOOST,
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IT_OCP_SWOUT,
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IT_OCP_OTG,
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IT_CURLIM_BUCK4,
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IT_CURLIM_BUCK3,
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IT_CURLIM_BUCK2,
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IT_CURLIM_BUCK1,
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/* Interrupt Register 3 (0x52 for latch) */
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IT_SHORT_SWOUT,
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IT_SHORT_SWOTG,
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IT_CURLIM_LDO6,
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IT_CURLIM_LDO5,
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IT_CURLIM_LDO4,
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IT_CURLIM_LDO3,
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IT_CURLIM_LDO2,
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IT_CURLIM_LDO1,
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/* Interrupt Register 3 (0x52 for latch) */
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IT_SWIN_R,
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IT_SWIN_F,
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IT_RESERVED_1,
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IT_RESERVED_2,
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IT_VINLOW_R,
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IT_VINLOW_F,
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IT_TWARN_R,
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IT_TWARN_F,
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IRQ_NR,
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} PMIC_IRQn;
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/* Private typedef -----------------------------------------------------------*/
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typedef struct {
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PMIC_RegulId_TypeDef id;
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uint16_t *voltage_table;
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uint8_t voltage_table_size;
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uint8_t control_reg;
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uint8_t low_power_reg;
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uint8_t rank ;
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uint8_t nvm_info ;
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} regul_struct;
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/* Those define should reflect NVM_USER section
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* For ES Eval Configuration this is specified as
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* 0xF7,
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0x92,
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0xC0,
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0x02,
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0xFA,
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0x30,
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0x00,
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0x33,
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* */
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#define NVM_SECTOR3_REGISTER_0 0xF7
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#define NVM_SECTOR3_REGISTER_1 0x92
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#define NVM_SECTOR3_REGISTER_2 0xC0
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#define NVM_SECTOR3_REGISTER_3 0x02
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#define NVM_SECTOR3_REGISTER_4 0xFA
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#define NVM_SECTOR3_REGISTER_5 0x30
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#define NVM_SECTOR3_REGISTER_6 0x00
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#define NVM_SECTOR3_REGISTER_7 0x33
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/* nvm_vinok_hyst: VINOK hysteresis voltage
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00: 200mV
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01: 300mV
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10: 400mV
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11: 500mV
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*
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* nvm_vinok: VINOK threshold voltage
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00: 3.1v
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01: 3.3v
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10: 3.5v
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11: 4.5v
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Otp_ldo4_forced :
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0: LDO4 ranks following OTP_RANK_LDO4<1:0>
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if VBUS_OTG or SWOUT is turn ON condition
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1: LDO4 follows normal ranking procedure
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nvm_longkeypress:
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0: Turn OFF on long key press inactive
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1: Turn OFF on long key press active
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nvm_autoturnon:
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0: PMIC does not start automatically on VIN rising
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1: PMIC starts automatically on VIN rising
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nvm_cc_keepoff :
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0: short circuit does not turn OFF PMIC
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1: short circuit turn OFF PMIC and keep it OFF till CC_flag is reset
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*
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*/
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#define OTP_VINOK_HYST ((NVM_SECTOR3_REGISTER_0 & 0xC0) >> 6) // nvm_vinok_hyst
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#define OTP_VINOK ((NVM_SECTOR3_REGISTER_0 & 0x30) >> 4) // nvm_vinok
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#define OTP_LDO4_FORCED ((NVM_SECTOR3_REGISTER_0 & 0x08) >> 3) // Otp_ldo4_forced
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#define OTP_LONGKEYPRESSED ((NVM_SECTOR3_REGISTER_0 & 0x04) >> 2) // nvm_longkeypress
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#define OTP_AUTOTURNON ((NVM_SECTOR3_REGISTER_0 & 0x02) >> 1) // nvm_autoturnon
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#define OTP_CC_KEEPOFF ((NVM_SECTOR3_REGISTER_0 & 0x01)) // nvm_cc_keepoff
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/*
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* nvm_rank_buck4:
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00: rank0
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01: rank1
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10: rank2
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11: rank3
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nvm_rank_buck3:
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00: rank0
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01: rank1
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10: rank2
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11: rank3
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nvm_rank_buck2:
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00: rank0
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01: rank1
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10: rank2
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11: rank3
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nvm_rank_buck1:
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00: rank0
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01: rank1
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10: rank2
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11: rank3
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*
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*/
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#define OTP_RANK_BUCK4 ((NVM_SECTOR3_REGISTER_1 & 0xC0) >> 6) // nvm_rank_buck4
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#define OTP_RANK_BUCK3 ((NVM_SECTOR3_REGISTER_1 & 0x30) >> 4) // nvm_rank_buck3
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#define OTP_RANK_BUCK2 ((NVM_SECTOR3_REGISTER_1 & 0x0C) >> 2) // nvm_rank_buck2
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#define OTP_RANK_BUCK1 ((NVM_SECTOR3_REGISTER_1 & 0x03)) // nvm_rank_buck1
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/*
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* nvm_rank_ldo4:
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00: rank0
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01: rank1
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10: rank2
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11: rank3
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nvm_rank_ldo3:
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00: rank0
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01: rank1
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10: rank2
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11: rank3
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nvm_rank_ldo2:
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00: rank0
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01: rank1
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10: rank2
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11: rank3
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nvm_rank_ldo1:
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00: rank0
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01: rank1
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10: rank2
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11: rank3
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*
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*/
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#define OTP_RANK_LDO4 ((NVM_SECTOR3_REGISTER_2 & 0xC0) >> 6) // nvm_rank_ldo4
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#define OTP_RANK_LDO3 ((NVM_SECTOR3_REGISTER_2 & 0x30) >> 4) // nvm_rank_ldo3
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#define OTP_RANK_LDO2 ((NVM_SECTOR3_REGISTER_2 & 0x0C) >> 2) // nvm_rank_ldo2
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#define OTP_RANK_LDO1 ((NVM_SECTOR3_REGISTER_2 & 0x03)) // nvm_rank_ldo1
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/*
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* nvm_clamp_output_buck: Clamp output value to 1.3V max
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0: output_buck4<5:0> not clamped
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1: output_buck4<5:0> to b011100(1.3V)
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nvm_bypass_mode_ldo3: LDO3 forced bypass mode
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0: LDO3 not in bypass mode
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1: LDO3 in bypass mode
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nvm_rank_vrefddr:
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00: rank0
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01: rank1
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10: rank2
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11: rank3
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nvm_rank_ldo6:
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00: rank0
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01: rank1
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10: rank2
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11: rank3
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nvm_rank_ldo5:
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00: rank0
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01: rank1
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10: rank2
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11: rank3
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*
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*/
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#define OTP_CLAMP_OUTPUT_BUCK4 ((NVM_SECTOR3_REGISTER_3 & 0x80) >> 7) // nvm_clamp_output_buck4
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#define OTP_BYPASS_MODE_LDO3 ((NVM_SECTOR3_REGISTER_3 & 0x40) >> 6) // nvm_bypass_mode_ldo3
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#define OTP_RANK_VREFDDR ((NVM_SECTOR3_REGISTER_3 & 0x30) >> 4) // nvm_rank_vrefddr
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#define OTP_RANK_LDO6 ((NVM_SECTOR3_REGISTER_3 & 0x0C) >> 2) // nvm_rank_ldo6
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#define OTP_RANK_LDO5 ((NVM_SECTOR3_REGISTER_3 & 0x03)) // nvm_rank_ldo5
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/*
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* nvm_output_buck4: Buck4 default output selection
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00: 1.15V
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01: 1.2V
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10: 1.8V
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11: 3.3V
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nvm_output_buck3: Buck3 default output selection
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00: 1.2V
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01: 1.8V
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10: 3.0V
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11: 3.3V
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nvm_output_buck2: Buck2 default output selection
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00: 1.1V
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01: 1.2V
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10: 1.35V
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11: 1.5V
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nvm_output_buck1: Buck1 default output selection
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00: 1.1V
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01: 1.15V
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10: 1.2V
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11: 1.25V
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*
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*/
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#define OTP_OUTPUT_BUCK4 ((NVM_SECTOR3_REGISTER_4 & 0xC0) >> 6) // nvm_output_buck4
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#define OTP_OUTPUT_BUCK3 ((NVM_SECTOR3_REGISTER_4 & 0x30) >> 4) // nvm_output_buck3
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#define OTP_OUTPUT_BUCK2 ((NVM_SECTOR3_REGISTER_4 & 0x0C) >> 2) // nvm_output_buck2
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#define OTP_OUTPUT_BUCK1 ((NVM_SECTOR3_REGISTER_4 & 0x03)) // nvm_output_buck1
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/*
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* [7] OTP_SWOFF_BY_BOOST_OVP:
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0 -> SWOUT will not turnoff bu boost OVP
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1 -> SWOUT will be turnoff by BOOST OVP
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[6] reserved
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[5:4] nvm_output_ldo3: LDO3 default output selection
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00: 1.8V
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01: 2.5V
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10: 3.3V
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11: output_buck2<4:0>/2 (VTT termination for DDR3 x32, Analog divider implemented in Analog)
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[3:2] nvm_output_ldo2: LDO2 default output selection
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00: 1.8V
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01: 2.5V
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10: 2.9V
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11: 3.3V
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[1:0] nvm_output_ldo1: LDO1 default output selection
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00: 1.8V
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01: 2.5V
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10: 2.9V
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11: 3.3V
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*
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*/
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#define OTP_SWOFF_BY_BOOST_OVP ((NVM_SECTOR3_REGISTER_5 & 0x80) >> 7) // OTP_SWOFF_BY_BOOST_OVP
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#define OTP_OUTPUT_LDO3 ((NVM_SECTOR3_REGISTER_5 & 0x30) >> 4) // nvm_output_ldo3
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#define OTP_OUTPUT_LDO2 ((NVM_SECTOR3_REGISTER_5 & 0x0C) >> 2) // nvm_output_ldo2
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#define OTP_OUTPUT_LDO1 ((NVM_SECTOR3_REGISTER_5 & 0x03)) // nvm_output_ldo1
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/*
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* [7:4] reserved
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*
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[3:2] nvm_output_ldo6: LDO6 default output selection
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00: 1.0V
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01: 1.2V
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10: 1.8V
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11: 3.3V
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[1:0] nvm_output_ldo5: LDO5 default output selection
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00: 1.8V
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01: 2.5V
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10: 2.9V
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11 : 3.3V
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*
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*/
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#define OTP_OUTPUT_LDO6 ((NVM_SECTOR3_REGISTER_6 & 0x0C) >> 2) // nvm_output_ldo6
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#define OTP_OUTPUT_LDO5 ((NVM_SECTOR3_REGISTER_6 & 0x03)) // nvm_output_ldo5
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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#define BIT(_x) (1UL << (_x))
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#define STM32_PMIC_NUM_IRQ_REGS 4
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#define TURN_ON_REG 0x1
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#define TURN_OFF_REG 0x2
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#define ICC_LDO_TURN_OFF_REG 0x3
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#define ICC_BUCK_TURN_OFF_REG 0x4
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#define RESET_STATUS_REG 0x5
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#define VERSION_STATUS_REG 0x6
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#define MAIN_CONTROL_REG 0x10
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#define PADS_PULL_REG 0x11
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#define BUCK_PULL_DOWN_REG 0x12
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#define LDO14_PULL_DOWN_REG 0x13
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#define LDO56_PULL_DOWN_REG 0x14
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#define VIN_CONTROL_REG 0x15
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#define PONKEY_TIMER_REG 0x16
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#define MASK_RANK_BUCK_REG 0x17
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#define MASK_RESET_BUCK_REG 0x18
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#define MASK_RANK_LDO_REG 0x19
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#define MASK_RESET_LDO_REG 0x1A
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#define WATCHDOG_CONTROL_REG 0x1B
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#define WATCHDOG_TIMER_REG 0x1C
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#define BUCK_ICC_TURNOFF_REG 0x1D
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#define LDO_ICC_TURNOFF_REG 0x1E
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#define BUCK_APM_CONTROL_REG 0x1F
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#define BUCK1_CONTROL_REG 0x20
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#define BUCK2_CONTROL_REG 0x21
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#define BUCK3_CONTROL_REG 0x22
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#define BUCK4_CONTROL_REG 0x23
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#define VREF_DDR_CONTROL_REG 0x24
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#define LDO1_CONTROL_REG 0x25
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#define LDO2_CONTROL_REG 0x26
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#define LDO3_CONTROL_REG 0x27
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#define LDO4_CONTROL_REG 0x28
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#define LDO5_CONTROL_REG 0x29
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#define LDO6_CONTROL_REG 0x2A
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#define BUCK1_PWRCTRL_REG 0x30
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#define BUCK2_PWRCTRL_REG 0x31
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#define BUCK3_PWRCTRL_REG 0x32
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#define BUCK4_PWRCTRL_REG 0x33
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#define VREF_DDR_PWRCTRL_REG 0x34
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#define LDO1_PWRCTRL_REG 0x35
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#define LDO2_PWRCTRL_REG 0x36
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#define LDO3_PWRCTRL_REG 0x37
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#define LDO4_PWRCTRL_REG 0x38
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#define LDO5_PWRCTRL_REG 0x39
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#define LDO6_PWRCTRL_REG 0x3A
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#define FREQUENCY_SPREADING_REG 0x3B
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#define USB_CONTROL_REG 0x40
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#define ITLATCH1_REG 0x50
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#define ITLATCH2_REG 0x51
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#define ITLATCH3_REG 0x52
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#define ITLATCH4_REG 0x53
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#define ITSETLATCH1_REG 0x60
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#define ITSETLATCH2_REG 0x61
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#define ITSETLATCH3_REG 0x62
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#define ITSETLATCH4_REG 0x63
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#define ITCLEARLATCH1_REG 0x70
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#define ITCLEARLATCH2_REG 0x71
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#define ITCLEARLATCH3_REG 0x72
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#define ITCLEARLATCH4_REG 0x73
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#define ITMASK1_REG 0x80
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#define ITMASK2_REG 0x81
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#define ITMASK3_REG 0x82
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#define ITMASK4_REG 0x83
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#define ITSETMASK1_REG 0x90
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#define ITSETMASK2_REG 0x91
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#define ITSETMASK3_REG 0x92
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#define ITSETMASK4_REG 0x93
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#define ITCLEARMASK1_REG 0xA0
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#define ITCLEARMASK2_REG 0xA1
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#define ITCLEARMASK3_REG 0xA2
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#define ITCLEARMASK4_REG 0xA3
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#define ITSOURCE1_REG 0xB0
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#define ITSOURCE2_REG 0xB1
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#define ITSOURCE3_REG 0xB2
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#define ITSOURCE4_REG 0xB3
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#define LDO_VOLTAGE_MASK 0x7C
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#define BUCK_VOLTAGE_MASK 0xFC
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#define LDO_BUCK_VOLTAGE_SHIFT 2
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#define LDO_ENABLE_MASK 0x01
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#define BUCK_ENABLE_MASK 0x01
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#define BUCK_HPLP_ENABLE_MASK 0x02
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#define LDO_HPLP_ENABLE_MASK 0x02
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#define LDO_BUCK_HPLP_SHIFT 1
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#define LDO_BUCK_RANK_MASK 0x01
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#define LDO_BUCK_RESET_MASK 0x01
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#define LDO_BUCK_PULL_DOWN_MASK 0x03
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/* Main PMIC Control Register
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* MAIN_CONTROL_REG
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* Address : 0x10
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* */
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#define ICC_EVENT_ENABLED BIT(4)
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#define PWRCTRL_POLARITY_HIGH BIT(3)
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#define PWRCTRL_PIN_VALID BIT(2)
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#define RESTART_REQUEST_ENABLED BIT(1)
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#define SOFTWARE_SWITCH_OFF_ENABLED BIT(0)
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/* Main PMIC PADS Control Register
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* PADS_PULL_REG
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* Address : 0x11
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* */
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#define WAKEUP_DETECTOR_DISABLED BIT(4)
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#define PWRCTRL_PD_ACTIVE BIT(3)
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#define PWRCTRL_PU_ACTIVE BIT(2)
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#define WAKEUP_PD_ACTIVE BIT(1)
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#define PONKEY_PU_ACTIVE BIT(0)
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/* Main PMIC VINLOW Control Register
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* VIN_CONTROL_REGC DMSC
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* Address : 0x15
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* */
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#define SWIN_DETECTOR_ENABLED BIT(7)
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#define SWOUT_DETECTOR_ENABLED BIT(6)
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#define VINLOW_HYST_MASK 0x3
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#define VINLOW_HYST_SHIFT 4
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#define VINLOW_THRESHOLD_MASK 0x7
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#define VINLOW_THRESHOLD_SHIFT 1
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#define VINLOW_ENABLED 0x01
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#define VINLOW_CTRL_REG_MASK 0xFF
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/* USB Control Register
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* Address : 0x40
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* */
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#define BOOST_OVP_DISABLED BIT(7)
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#define VBUS_OTG_DETECTION_DISABLED BIT(6)
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// Discharge not implemented
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#define OCP_LIMIT_HIGH BIT(3)
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#define SWIN_SWOUT_ENABLED BIT(2)
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#define USBSW_OTG_SWITCH_ENABLED BIT(1)
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/* IRQ masks */
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/* Interrupt Mask for Register 1 (0x50 for latch) */
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#define IT_SWOUT_R_MASK BIT(7)
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#define IT_SWOUT_F_MASK BIT(6)
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#define IT_VBUS_OTG_R_MASK BIT(5)
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#define IT_VBUS_OTG_F_MASK BIT(4)
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#define IT_WAKEUP_R_MASK BIT(3)
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#define IT_WAKEUP_F_MASK BIT(2)
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#define IT_PONKEY_R_MASK BIT(1)
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#define IT_PONKEY_F_MASK BIT(0)
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/* Interrupt Mask for Register 2 (0x51 for latch) */
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#define IT_OVP_BOOST_MASK BIT(7)
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#define IT_OCP_BOOST_MASK BIT(6)
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#define IT_OCP_SWOUT_MASK BIT(5)
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#define IT_OCP_OTG_MASK BIT(4)
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#define IT_CURLIM_BUCK4_MASK BIT(3)
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#define IT_CURLIM_BUCK3_MASK BIT(2)
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#define IT_CURLIM_BUCK2_MASK BIT(1)
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#define IT_CURLIM_BUCK1_MASK BIT(0)
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/* Interrupt Mask for Register 3 (0x52 for latch) */
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#define IT_SHORT_SWOUT_MASK BIT(7)
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#define IT_SHORT_SWOTG_MASK BIT(6)
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#define IT_CURLIM_LDO6_MASK BIT(5)
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#define IT_CURLIM_LDO5_MASK BIT(4)
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#define IT_CURLIM_LDO4_MASK BIT(3)
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#define IT_CURLIM_LDO3_MASK BIT(2)
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#define IT_CURLIM_LDO2_MASK BIT(1)
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#define IT_CURLIM_LDO1_MASK BIT(0)
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/* Interrupt Mask for Register 4 (0x53 for latch) */
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#define IT_SWIN_R_MASK BIT(7)
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#define IT_SWIN_F_MASK BIT(6)
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/* Reserved 1 */
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/* Reserved 2 */
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#define IT_VINLOW_R_MASK BIT(3)
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#define IT_VINLOW_F_MASK BIT(2)
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#define IT_TWARN_R_MASK BIT(1)
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#define IT_TWARN_F_MASK BIT(0)
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#define PMIC_VERSION_ID 0x10
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#define STPMU1_I2C_ADDRESS (NVM_SECTOR3_REGISTER_7 & 0x7F)
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#ifdef __cplusplus
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}
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#endif
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#endif
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