929 lines
29 KiB
C
929 lines
29 KiB
C
/*
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* File : synopGMAC.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) chinesebear
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2017-08-24 chinesebear first version
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*/
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#include <rtthread.h>
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#include <rtdef.h>
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//#include <lwip/pbuf.h>
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#include "synopGMAC.h"
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#include "mii.c"
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#include "synopGMAC_debug.h"
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#include <ls1c.h>
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#define RMII
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#define Gmac_base 0xbfe10000
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#define Buffer_Size 2048
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#define MAX_ADDR_LEN 6
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#define NAMESIZE 16
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#define LS1B_GMAC0_IRQ 34
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#define BUS_SIZE_ALIGN(x) ((x+15)&~15)
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#define DEFAULT_MAC_ADDRESS {0x00, 0x55, 0x7B, 0xB5, 0x7D, 0xF7}
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u32 regbase = 0xbfe10000;
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static u32 GMAC_Power_down;
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extern void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u32 *addr) ;
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extern s32 synopGMAC_check_phy_init (synopGMACPciNetworkAdapter *adapter) ;
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extern int init_phy(synopGMACdevice *gmacdev);
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dma_addr_t plat_dma_map_single(void *hwdev, void *ptr,u32 size);
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void eth_rx_irq(int irqno,void *param);
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static char Rx_Buffer[Buffer_Size];
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static char Tx_Buffer[Buffer_Size];
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struct rt_eth_dev
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{
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struct eth_device parent;
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rt_uint8_t dev_addr[MAX_ADDR_LEN];
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char *name;
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int iobase;
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int state;
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int index;
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struct rt_timer link_timer;
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struct rt_timer rx_poll_timer;
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void *priv;
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};
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static struct rt_eth_dev eth_dev;
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static struct rt_semaphore sem_ack, sem_lock;
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/**
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* This sets up the transmit Descriptor queue in ring or chain mode.
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* This function is tightly coupled to the platform and operating system
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* Device is interested only after the descriptors are setup. Therefore this function
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* is not included in the device driver API. This function should be treated as an
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* example code to design the descriptor structures for ring mode or chain mode.
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* This function depends on the pcidev structure for allocation consistent dma-able memory in case
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* of linux.
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* This limitation is due to the fact that linux uses pci structure to allocate a dmable memory
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* - Allocates the memory for the descriptors.
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* - Initialize the Busy and Next descriptors indices to 0(Indicating first descriptor).
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* - Initialize the Busy and Next descriptors to first descriptor address.
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* - Initialize the last descriptor with the endof ring in case of ring mode.
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* - Initialize the descriptors in chain mode.
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* @param[in] pointer to synopGMACdevice.
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* @param[in] pointer to pci_device structure.
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* @param[in] number of descriptor expected in tx descriptor queue.
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* @param[in] whether descriptors to be created in RING mode or CHAIN mode.
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* \return 0 upon success. Error code upon failure.
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* \note This function fails if allocation fails for required number of descriptors in Ring mode,
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* but in chain mode
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* function returns -ESYNOPGMACNOMEM in the process of descriptor chain creation. once returned from
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* this function
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* user should for gmacdev->TxDescCount to see how many descriptors are there in the chain. Should
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* continue further
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* only if the number of descriptors in the chain meets the requirements
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*/
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s32 synopGMAC_setup_tx_desc_queue(synopGMACdevice * gmacdev,u32 no_of_desc, u32 desc_mode)
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{
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s32 i;
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DmaDesc * bf1;
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DmaDesc *first_desc = NULL;
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dma_addr_t dma_addr;
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gmacdev->TxDescCount = 0;
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first_desc = (DmaDesc *)plat_alloc_consistent_dmaable_memory (gmacdev, sizeof(DmaDesc) * no_of_desc,&dma_addr);
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if(first_desc == NULL){
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rt_kprintf("Error in Tx Descriptors memory allocation\n");
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return -ESYNOPGMACNOMEM;
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}
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DEBUG_MES("tx_first_desc_addr = %p\n", first_desc);
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DEBUG_MES("dmaadr = %p\n", dma_addr);
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gmacdev->TxDescCount = no_of_desc;
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gmacdev->TxDesc = first_desc;
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gmacdev->TxDescDma = dma_addr;
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for(i =0; i < gmacdev->TxDescCount; i++){
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synopGMAC_tx_desc_init_ring(gmacdev->TxDesc + i, i == gmacdev->TxDescCount-1);
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#if SYNOP_TOP_DEBUG
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rt_kprintf("\n%02d %08x \n",i,(unsigned int)(gmacdev->TxDesc + i));
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rt_kprintf("%08x ",(unsigned int)((gmacdev->TxDesc + i))->status);
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rt_kprintf("%08x ",(unsigned int)((gmacdev->TxDesc + i)->length));
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rt_kprintf("%08x ",(unsigned int)((gmacdev->TxDesc + i)->buffer1));
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rt_kprintf("%08x ",(unsigned int)((gmacdev->TxDesc + i)->buffer2));
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rt_kprintf("%08x ",(unsigned int)((gmacdev->TxDesc + i)->data1));
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rt_kprintf("%08x ",(unsigned int)((gmacdev->TxDesc + i)->data2));
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rt_kprintf("%08x ",(unsigned int)((gmacdev->TxDesc + i)->dummy1));
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rt_kprintf("%08x ",(unsigned int)((gmacdev->TxDesc + i)->dummy2));
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#endif
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}
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gmacdev->TxNext = 0;
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gmacdev->TxBusy = 0;
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gmacdev->TxNextDesc = gmacdev->TxDesc;
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gmacdev->TxBusyDesc = gmacdev->TxDesc;
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gmacdev->BusyTxDesc = 0;
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return -ESYNOPGMACNOERR;
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}
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/**
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* This sets up the receive Descriptor queue in ring or chain mode.
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* This function is tightly coupled to the platform and operating system
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* Device is interested only after the descriptors are setup. Therefore this function
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* is not included in the device driver API. This function should be treated as an
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* example code to design the descriptor structures in ring mode or chain mode.
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* This function depends on the pcidev structure for allocation of consistent dma-able memory in
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* case of linux.
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* This limitation is due to the fact that linux uses pci structure to allocate a dmable memory
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* - Allocates the memory for the descriptors.
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* - Initialize the Busy and Next descriptors indices to 0(Indicating first descriptor).
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* - Initialize the Busy and Next descriptors to first descriptor address.
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* - Initialize the last descriptor with the endof ring in case of ring mode.
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* - Initialize the descriptors in chain mode.
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* @param[in] pointer to synopGMACdevice.
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* @param[in] pointer to pci_device structure.
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* @param[in] number of descriptor expected in rx descriptor queue.
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* @param[in] whether descriptors to be created in RING mode or CHAIN mode.
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* \return 0 upon success. Error code upon failure.
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* \note This function fails if allocation fails for required number of descriptors in Ring mode,
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* but in chain mode
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* function returns -ESYNOPGMACNOMEM in the process of descriptor chain creation. once returned from
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* this function
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* user should for gmacdev->RxDescCount to see how many descriptors are there in the chain. Should
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* continue further
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* only if the number of descriptors in the chain meets the requirements
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*/
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s32 synopGMAC_setup_rx_desc_queue(synopGMACdevice * gmacdev,u32 no_of_desc, u32 desc_mode)
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{
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s32 i;
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DmaDesc * bf1;
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DmaDesc *first_desc = NULL;
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dma_addr_t dma_addr;
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gmacdev->RxDescCount = 0;
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first_desc =(DmaDesc *)plat_alloc_consistent_dmaable_memory (gmacdev, sizeof(DmaDesc) * no_of_desc, &dma_addr);
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if(first_desc == NULL){
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rt_kprintf("Error in Rx Descriptor Memory allocation in Ring mode\n");
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return -ESYNOPGMACNOMEM;
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}
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DEBUG_MES("rx_first_desc_addr = %p\n", first_desc);
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DEBUG_MES("dmaadr = %p\n", dma_addr);
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gmacdev->RxDescCount = no_of_desc;
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gmacdev->RxDesc = (DmaDesc *)first_desc;
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gmacdev->RxDescDma = dma_addr;
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for(i =0; i < gmacdev->RxDescCount; i++){
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synopGMAC_rx_desc_init_ring(gmacdev->RxDesc + i, i == gmacdev->RxDescCount-1);
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}
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gmacdev->RxNext = 0;
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gmacdev->RxBusy = 0;
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gmacdev->RxNextDesc = gmacdev->RxDesc;
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gmacdev->RxBusyDesc = gmacdev->RxDesc;
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gmacdev->BusyRxDesc = 0;
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return -ESYNOPGMACNOERR;
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}
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void synopGMAC_linux_cable_unplug_function(void *adaptr)
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{
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s32 data;
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synopGMACPciNetworkAdapter *adapter = (synopGMACPciNetworkAdapter *)adaptr;
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synopGMACdevice *gmacdev = adapter->synopGMACdev;
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struct ethtool_cmd cmd;
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//rt_kprintf("%s\n",__FUNCTION__);
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if(!mii_link_ok(&adapter->mii)){
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if(gmacdev->LinkState)
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rt_kprintf("\r\nNo Link\r\n");
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gmacdev->DuplexMode = 0;
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gmacdev->Speed = 0;
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gmacdev->LoopBackMode = 0;
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gmacdev->LinkState = 0;
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}
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else{
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data = synopGMAC_check_phy_init(adapter);
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if(gmacdev->LinkState != data){
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gmacdev->LinkState = data;
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synopGMAC_mac_init(gmacdev);
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rt_kprintf("Link is up in %s mode\n",(gmacdev->DuplexMode == FULLDUPLEX) ? "FULL DUPLEX": "HALF DUPLEX");
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if(gmacdev->Speed == SPEED1000)
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rt_kprintf("Link is with 1000M Speed \r\n");
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if(gmacdev->Speed == SPEED100)
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rt_kprintf("Link is with 100M Speed \n");
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if(gmacdev->Speed == SPEED10)
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rt_kprintf("Link is with 10M Speed \n");
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}
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}
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}
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s32 synopGMAC_check_phy_init (synopGMACPciNetworkAdapter *adapter)
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{
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struct ethtool_cmd cmd;
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synopGMACdevice *gmacdev = adapter->synopGMACdev;
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if(!mii_link_ok(&adapter->mii))
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{
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gmacdev->DuplexMode = FULLDUPLEX;
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gmacdev->Speed = SPEED100;
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return 0;
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}
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else
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{
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mii_ethtool_gset(&adapter->mii, &cmd);
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gmacdev->DuplexMode = (cmd.duplex == DUPLEX_FULL) ? FULLDUPLEX: HALFDUPLEX ;
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if(cmd.speed == SPEED_1000)
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gmacdev->Speed = SPEED1000;
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else if(cmd.speed == SPEED_100)
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gmacdev->Speed = SPEED100;
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else
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gmacdev->Speed = SPEED10;
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}
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return gmacdev->Speed|(gmacdev->DuplexMode<<4);
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}
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static int Mac_change_check(u8 *macaddr0, u8 *macaddr1)
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{
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int i;
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for(i = 0; i < 6; i++){
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if(macaddr0[i] != macaddr1[i])
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return 1;
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}
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return 0;
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}
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static rt_err_t eth_init(rt_device_t device )
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{
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struct eth_device *eth_device = (struct eth_device *)device;
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RT_ASSERT(eth_device != RT_NULL);
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s32 ijk;
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s32 status = 0;
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u64 dma_addr;
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u32 Mac_changed = 0;
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struct pbuf *pbuf;
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u8 macaddr[6] = DEFAULT_MAC_ADDRESS;
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struct rt_eth_dev *dev = ð_dev;
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struct synopGMACNetworkAdapter *adapter = dev->priv;
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synopGMACdevice * gmacdev = (synopGMACdevice *)adapter->synopGMACdev;
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synopGMAC_reset(gmacdev);
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synopGMAC_attach(gmacdev,(regbase + MACBASE),(regbase + DMABASE), DEFAULT_PHY_BASE, macaddr);
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synopGMAC_read_version(gmacdev);
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synopGMAC_set_mdc_clk_div(gmacdev,GmiiCsrClk3);
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gmacdev->ClockDivMdc = synopGMAC_get_mdc_clk_div(gmacdev);
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init_phy(adapter->synopGMACdev);
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rt_kprintf("tx desc_queue\n");
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synopGMAC_setup_tx_desc_queue(gmacdev,TRANSMIT_DESC_SIZE, RINGMODE);
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synopGMAC_init_tx_desc_base(gmacdev);
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rt_kprintf("rx desc_queue\n");
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synopGMAC_setup_rx_desc_queue(gmacdev,RECEIVE_DESC_SIZE, RINGMODE);
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synopGMAC_init_rx_desc_base(gmacdev);
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DEBUG_MES("DmaRxBaseAddr = %08x\n",synopGMACReadReg(gmacdev->DmaBase,DmaRxBaseAddr));
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// u32 dmaRx_Base_addr = synopGMACReadReg(gmacdev->DmaBase,DmaRxBaseAddr);
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// rt_kprintf("first_desc_addr = 0x%x\n", dmaRx_Base_addr);
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#ifdef ENH_DESC_8W
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synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength32 | DmaDescriptorSkip2 | DmaDescriptor8Words );
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#else
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//synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength4 | DmaDescriptorSkip1);
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synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength4 | DmaDescriptorSkip2);
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#endif
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synopGMAC_dma_control_init(gmacdev,DmaStoreAndForward |DmaTxSecondFrame|DmaRxThreshCtrl128);
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status = synopGMAC_check_phy_init(adapter);
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synopGMAC_mac_init(gmacdev);
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synopGMAC_pause_control(gmacdev);
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#ifdef IPC_OFFLOAD
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synopGMAC_enable_rx_chksum_offload(gmacdev);
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synopGMAC_rx_tcpip_chksum_drop_enable(gmacdev);
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#endif
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u32 skb;
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do{
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skb = (u32)plat_alloc_memory(RX_BUF_SIZE); //should skb aligned here?
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if(skb == RT_NULL){
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rt_kprintf("ERROR in skb buffer allocation\n");
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break;
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}
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dma_addr = plat_dma_map_single(gmacdev,(void *)skb,RX_BUF_SIZE); //获取 skb 的 dma 地址
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status = synopGMAC_set_rx_qptr(gmacdev,dma_addr,RX_BUF_SIZE,(u32)skb,0,0,0);
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if(status < 0)
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{
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rt_kprintf("status < 0!!\n");
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plat_free_memory((void *)skb);
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}
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}while(status >= 0 && (status < (RECEIVE_DESC_SIZE - 1)));
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synopGMAC_clear_interrupt(gmacdev);
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synopGMAC_disable_mmc_tx_interrupt(gmacdev, 0xFFFFFFFF);
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synopGMAC_disable_mmc_rx_interrupt(gmacdev, 0xFFFFFFFF);
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synopGMAC_disable_mmc_ipc_rx_interrupt(gmacdev, 0xFFFFFFFF);
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// synopGMAC_disable_interrupt_all(gmacdev);
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synopGMAC_enable_interrupt(gmacdev, DmaIntEnable);
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synopGMAC_enable_dma_rx(gmacdev);
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synopGMAC_enable_dma_tx(gmacdev);
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plat_delay(DEFAULT_LOOP_VARIABLE);
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synopGMAC_check_phy_init(adapter);
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synopGMAC_mac_init(gmacdev);
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rt_timer_init(&dev->link_timer, "link_timer",
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synopGMAC_linux_cable_unplug_function,
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(void *)adapter,
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RT_TICK_PER_SECOND,
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RT_TIMER_FLAG_PERIODIC);
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rt_timer_start(&dev->link_timer);
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#ifdef RT_USING_GMAC_INT_MODE
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/* installl isr */
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DEBUG_MES("%s\n", __FUNCTION__);
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rt_hw_interrupt_install(LS1C_MAC_IRQ, eth_rx_irq, RT_NULL, "e0_isr");
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rt_hw_interrupt_umask(LS1C_MAC_IRQ);
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#else
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rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer",
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eth_rx_irq,
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(void *)adapter,
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1,
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RT_TIMER_FLAG_PERIODIC);
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rt_timer_start(&dev->rx_poll_timer);
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#endif /*RT_USING_GMAC_INT_MODE*/
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rt_kprintf("eth_inited!\n");
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return RT_EOK;
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}
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static rt_err_t eth_open(rt_device_t dev, rt_uint16_t oflag)
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{
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rt_kprintf("eth_open!!\n");
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return RT_EOK;
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}
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static rt_err_t eth_close(rt_device_t dev)
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{
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return RT_EOK;
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}
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static rt_size_t eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
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{
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_size_t eth_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
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{
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_err_t eth_control(rt_device_t dev, int cmd, void *args)
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{
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switch (cmd)
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{
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case NIOCTL_GADDR:
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if(args) rt_memcpy(args, eth_dev.dev_addr, 6);
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else return -RT_ERROR;
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break;
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default :
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break;
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}
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return RT_EOK;
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}
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rt_err_t rt_eth_tx(rt_device_t device, struct pbuf* p)
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{
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/* lock eth device */
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rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
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DEBUG_MES("in %s\n", __FUNCTION__);
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s32 status;
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u32 pbuf;
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u64 dma_addr;
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u32 offload_needed = 0;
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u32 index;
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DmaDesc * dpr;
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struct rt_eth_dev *dev = (struct rt_eth_dev *) device;
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struct synopGMACNetworkAdapter *adapter;
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synopGMACdevice * gmacdev;
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adapter = (struct synopGMACNetworkAdapter *) dev->priv;
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if(adapter == NULL)
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return -1;
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|
|
|
gmacdev = (synopGMACdevice *) adapter->synopGMACdev;
|
|
if(gmacdev == NULL)
|
|
return -1;
|
|
|
|
if(!synopGMAC_is_desc_owned_by_dma(gmacdev->TxNextDesc))
|
|
{
|
|
|
|
pbuf = (u32)plat_alloc_memory(p->len);
|
|
//pbuf = (u32)pbuf_alloc(PBUF_LINK, p->len, PBUF_RAM);
|
|
if(pbuf == 0)
|
|
{
|
|
rt_kprintf("===error in alloc bf1\n");
|
|
return -1;
|
|
}
|
|
|
|
DEBUG_MES("p->len = %d\n", p->len);
|
|
memcpy((void *)pbuf, p->payload, p->len);
|
|
dma_addr = plat_dma_map_single(gmacdev,(void*)pbuf,p->len);
|
|
|
|
status = synopGMAC_set_tx_qptr(gmacdev,dma_addr,p->len,pbuf,0,0,0,offload_needed,&index,dpr);
|
|
if(status < 0){
|
|
rt_kprintf("%s No More Free Tx Descriptors\n",__FUNCTION__);
|
|
|
|
plat_free_memory((void *)pbuf);
|
|
return -16;
|
|
}
|
|
}
|
|
synopGMAC_resume_dma_tx(gmacdev);
|
|
|
|
s32 desc_index;
|
|
u32 data1, data2;
|
|
u32 dma_addr1, dma_addr2;
|
|
u32 length1, length2;
|
|
#ifdef ENH_DESC_8W
|
|
u32 ext_status;
|
|
u16 time_stamp_higher;
|
|
u32 time_stamp_high;
|
|
u32 time_stamp_low;
|
|
#endif
|
|
do {
|
|
#ifdef ENH_DESC_8W
|
|
desc_index = synopGMAC_get_tx_qptr(gmacdev, &status, &dma_addr1, &length1, &data1, &dma_addr2, &length2, &data2,&ext_status,&time_stamp_high,&time_stamp_low);
|
|
synopGMAC_TS_read_timestamp_higher_val(gmacdev, &time_stamp_higher);
|
|
#else
|
|
desc_index = synopGMAC_get_tx_qptr(gmacdev, &status, &dma_addr1, &length1, &data1, &dma_addr2, &length2, &data2);
|
|
#endif
|
|
if(desc_index >= 0 && data1 != 0){
|
|
#ifdef IPC_OFFLOAD
|
|
if(synopGMAC_is_tx_ipv4header_checksum_error(gmacdev, status)){
|
|
rt_kprintf("Harware Failed to Insert IPV4 Header Checksum\n");
|
|
}
|
|
if(synopGMAC_is_tx_payload_checksum_error(gmacdev, status)){
|
|
rt_kprintf("Harware Failed to Insert Payload Checksum\n");
|
|
}
|
|
#endif
|
|
|
|
plat_free_memory((void *)(data1)); //sw: data1 = buffer1
|
|
|
|
if(synopGMAC_is_desc_valid(status)){
|
|
adapter->synopGMACNetStats.tx_bytes += length1;
|
|
adapter->synopGMACNetStats.tx_packets++;
|
|
}
|
|
else {
|
|
adapter->synopGMACNetStats.tx_errors++;
|
|
adapter->synopGMACNetStats.tx_aborted_errors += synopGMAC_is_tx_aborted(status);
|
|
adapter->synopGMACNetStats.tx_carrier_errors += synopGMAC_is_tx_carrier_error(status);
|
|
}
|
|
} adapter->synopGMACNetStats.collisions += synopGMAC_get_tx_collision_count(status);
|
|
} while(desc_index >= 0);
|
|
|
|
/* unlock eth device */
|
|
rt_sem_release(&sem_lock);
|
|
// rt_kprintf("output %d bytes\n", p->len);
|
|
u32 test_data;
|
|
test_data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus);
|
|
return RT_EOK;
|
|
}
|
|
|
|
struct pbuf *rt_eth_rx(rt_device_t device)
|
|
{
|
|
DEBUG_MES("%s : \n", __FUNCTION__);
|
|
struct rt_eth_dev *dev = ð_dev;
|
|
struct synopGMACNetworkAdapter *adapter;
|
|
synopGMACdevice * gmacdev;
|
|
// struct PmonInet * pinetdev;
|
|
s32 desc_index;
|
|
int i;
|
|
char * ptr;
|
|
u32 bf1;
|
|
u32 data1;
|
|
u32 data2;
|
|
u32 len;
|
|
u32 status;
|
|
u32 dma_addr1;
|
|
u32 dma_addr2;
|
|
struct pbuf *pbuf = RT_NULL;
|
|
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
|
|
|
|
adapter = (struct synopGMACNetworkAdapter *) dev->priv;
|
|
if(adapter == NULL){
|
|
rt_kprintf("%S : Unknown Device !!\n", __FUNCTION__);
|
|
return NULL;
|
|
}
|
|
|
|
gmacdev = (synopGMACdevice *) adapter->synopGMACdev;
|
|
if(gmacdev == NULL){
|
|
rt_kprintf("%s : GMAC device structure is missing\n", __FUNCTION__);
|
|
return NULL;
|
|
}
|
|
|
|
/*Handle the Receive Descriptors*/
|
|
// do{
|
|
desc_index = synopGMAC_get_rx_qptr(gmacdev, &status,&dma_addr1,NULL, &data1,&dma_addr2,NULL,&data2);
|
|
|
|
if(desc_index >= 0 && data1 != 0){
|
|
DEBUG_MES("Received Data at Rx Descriptor %d for skb 0x%08x whose status is %08x\n",desc_index,dma_addr1,status);
|
|
|
|
if(synopGMAC_is_rx_desc_valid(status)||SYNOP_PHY_LOOPBACK)
|
|
{
|
|
pbuf = pbuf_alloc(PBUF_LINK, MAX_ETHERNET_PAYLOAD, PBUF_RAM);
|
|
if(pbuf == 0) rt_kprintf("===error in pbuf_alloc\n");
|
|
|
|
|
|
dma_addr1 = plat_dma_map_single(gmacdev,(void*)data1,RX_BUF_SIZE);
|
|
len = synopGMAC_get_rx_desc_frame_length(status); //Not interested in Ethernet CRC bytes
|
|
rt_memcpy( pbuf->payload, (char *)data1, len);
|
|
DEBUG_MES("==get pkg len: %d\n",len);
|
|
}
|
|
else
|
|
{
|
|
rt_kprintf("s: %08x\n",status);
|
|
adapter->synopGMACNetStats.rx_errors++;
|
|
adapter->synopGMACNetStats.collisions += synopGMAC_is_rx_frame_collision(status);
|
|
adapter->synopGMACNetStats.rx_crc_errors += synopGMAC_is_rx_crc(status);
|
|
adapter->synopGMACNetStats.rx_frame_errors += synopGMAC_is_frame_dribbling_errors(status);
|
|
adapter->synopGMACNetStats.rx_length_errors += synopGMAC_is_rx_frame_length_errors(status);
|
|
}
|
|
|
|
desc_index = synopGMAC_set_rx_qptr(gmacdev,dma_addr1, RX_BUF_SIZE, (u32)data1,0,0,0);
|
|
|
|
if(desc_index < 0){
|
|
#if SYNOP_RX_DEBUG
|
|
rt_kprintf("Cannot set Rx Descriptor for data1 %08x\n",(u32)data1);
|
|
#endif
|
|
plat_free_memory((void *)data1);
|
|
}
|
|
|
|
}
|
|
|
|
// }while(desc_index >= 0);
|
|
rt_sem_release(&sem_lock);
|
|
DEBUG_MES("%s : before return \n", __FUNCTION__);
|
|
return pbuf;
|
|
}
|
|
|
|
static int rtl88e1111_config_init(synopGMACdevice *gmacdev)
|
|
{
|
|
int retval, err;
|
|
u16 data;
|
|
|
|
DEBUG_MES("in %s\n", __FUNCTION__);
|
|
synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x14,&data);
|
|
data = data | 0x82;
|
|
err = synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x14,data);
|
|
synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x00,&data);
|
|
data = data | 0x8000;
|
|
err = synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x00,data);
|
|
#if SYNOP_PHY_LOOPBACK
|
|
synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x14,&data);
|
|
data = data | 0x70;
|
|
data = data & 0xffdf;
|
|
err = synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x14,data);
|
|
data = 0x8000;
|
|
err = synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x00,data);
|
|
data = 0x5140;
|
|
err = synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x00,data);
|
|
#endif
|
|
if (err < 0)
|
|
return err;
|
|
return 0;
|
|
}
|
|
|
|
int init_phy(synopGMACdevice *gmacdev)
|
|
{
|
|
u16 data;
|
|
|
|
synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,2,&data);
|
|
/*set 88e1111 clock phase delay*/
|
|
if(data == 0x141)
|
|
rtl88e1111_config_init(gmacdev);
|
|
#if defined (RMII)
|
|
else if(data == 0x8201)
|
|
{
|
|
//RTL8201
|
|
data = 0x400; // set RMII mode
|
|
synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x19,data);
|
|
synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x19,&data);
|
|
TR("phy reg25 is %0x \n",data);
|
|
|
|
data = 0x3100; //set 100M speed
|
|
synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x0,data);
|
|
}
|
|
else if(data == 0x0180 || data == 0x0181)
|
|
{
|
|
//DM9161
|
|
synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x10,&data);
|
|
data |= (1 << 8); //set RMII mode
|
|
synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x10,data); //set RMII mode
|
|
synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x10,&data);
|
|
TR("phy reg16 is 0x%0x \n",data);
|
|
|
|
// synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x0,&data);
|
|
// data &= ~(1<<10);
|
|
data = 0x3100; //set auto-
|
|
//data = 0x0100; //set 10M speed
|
|
synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x0,data);
|
|
}
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
u32 synopGMAC_wakeup_filter_config3[] = {
|
|
0x00000000,
|
|
0x000000FF,
|
|
0x00000000,
|
|
0x00000000,
|
|
0x00000100,
|
|
0x00003200,
|
|
0x7eED0000,
|
|
0x00000000
|
|
};
|
|
|
|
static void synopGMAC_linux_powerdown_mac(synopGMACdevice *gmacdev)
|
|
{
|
|
rt_kprintf("Put the GMAC to power down mode..\n");
|
|
|
|
GMAC_Power_down = 1;
|
|
|
|
synopGMAC_disable_dma_tx(gmacdev);
|
|
plat_delay(10000);
|
|
|
|
synopGMAC_tx_disable(gmacdev);
|
|
synopGMAC_rx_disable(gmacdev);
|
|
plat_delay(10000);
|
|
|
|
synopGMAC_disable_dma_rx(gmacdev);
|
|
|
|
synopGMAC_magic_packet_enable(gmacdev);
|
|
synopGMAC_write_wakeup_frame_register(gmacdev, synopGMAC_wakeup_filter_config3);
|
|
|
|
synopGMAC_wakeup_frame_enable(gmacdev);
|
|
|
|
synopGMAC_rx_enable(gmacdev);
|
|
|
|
synopGMAC_pmt_int_enable(gmacdev);
|
|
|
|
synopGMAC_power_down_enable(gmacdev);
|
|
return;
|
|
}
|
|
|
|
static void synopGMAC_linux_powerup_mac(synopGMACdevice *gmacdev)
|
|
{
|
|
GMAC_Power_down = 0;
|
|
if( synopGMAC_is_magic_packet_received(gmacdev))
|
|
rt_kprintf("GMAC wokeup due to Magic Pkt Received\n");
|
|
if(synopGMAC_is_wakeup_frame_received(gmacdev))
|
|
rt_kprintf("GMAC wokeup due to Wakeup Frame Received\n");
|
|
|
|
synopGMAC_pmt_int_disable(gmacdev);
|
|
|
|
synopGMAC_rx_enable(gmacdev);
|
|
synopGMAC_enable_dma_rx(gmacdev);
|
|
|
|
synopGMAC_tx_enable(gmacdev);
|
|
synopGMAC_enable_dma_tx(gmacdev);
|
|
return;
|
|
}
|
|
|
|
|
|
static int mdio_read(synopGMACPciNetworkAdapter *adapter, int addr, int reg)
|
|
{
|
|
synopGMACdevice * gmacdev;
|
|
u16 data;
|
|
gmacdev = adapter->synopGMACdev;
|
|
|
|
synopGMAC_read_phy_reg(gmacdev->MacBase,addr,reg, &data);
|
|
return data;
|
|
}
|
|
|
|
static void mdio_write(synopGMACPciNetworkAdapter *adapter, int addr, int reg, int data)
|
|
{
|
|
synopGMACdevice * gmacdev;
|
|
gmacdev = adapter->synopGMACdev;
|
|
synopGMAC_write_phy_reg(gmacdev->MacBase,addr,reg,data);
|
|
}
|
|
|
|
void eth_rx_irq(int irqno,void *param)
|
|
{
|
|
struct rt_eth_dev *dev = ð_dev;
|
|
struct synopGMACNetworkAdapter *adapter = dev->priv;
|
|
//DEBUG_MES("in irq!!\n");
|
|
#ifdef RT_USING_GMAC_INT_MODE
|
|
int i ;
|
|
for(i = 0; i < 7200; i++)
|
|
;
|
|
#endif /*RT_USING_GMAC_INT_MODE*/
|
|
synopGMACdevice * gmacdev = (synopGMACdevice *)adapter->synopGMACdev;
|
|
|
|
u32 interrupt,dma_status_reg;
|
|
s32 status;
|
|
u32 dma_addr;
|
|
|
|
//rt_kprintf("irq i = %d\n", i++);
|
|
dma_status_reg = synopGMACReadReg(gmacdev->DmaBase, DmaStatus);
|
|
if(dma_status_reg == 0)
|
|
{
|
|
rt_kprintf("dma_status ==0 \n");
|
|
return;
|
|
}
|
|
|
|
//rt_kprintf("dma_status_reg is 0x%x\n", dma_status_reg);
|
|
u32 gmacstatus;
|
|
synopGMAC_disable_interrupt_all(gmacdev);
|
|
gmacstatus = synopGMACReadReg(gmacdev->MacBase,GmacStatus);
|
|
|
|
if(dma_status_reg & GmacPmtIntr){
|
|
rt_kprintf("%s:: Interrupt due to PMT module\n",__FUNCTION__);
|
|
//synopGMAC_linux_powerup_mac(gmacdev);
|
|
}
|
|
if(dma_status_reg & GmacMmcIntr){
|
|
rt_kprintf("%s:: Interrupt due to MMC module\n",__FUNCTION__);
|
|
DEBUG_MES("%s:: synopGMAC_rx_int_status = %08x\n",__FUNCTION__,synopGMAC_read_mmc_rx_int_status(gmacdev));
|
|
DEBUG_MES("%s:: synopGMAC_tx_int_status = %08x\n",__FUNCTION__,synopGMAC_read_mmc_tx_int_status(gmacdev));
|
|
}
|
|
|
|
if(dma_status_reg & GmacLineIntfIntr){
|
|
rt_kprintf("%s:: Interrupt due to GMAC LINE module\n",__FUNCTION__);
|
|
}
|
|
|
|
interrupt = synopGMAC_get_interrupt_type(gmacdev);
|
|
//rt_kprintf("%s:Interrupts to be handled: 0x%08x\n",__FUNCTION__,interrupt);
|
|
if(interrupt & synopGMACDmaError){
|
|
u8 mac_addr0[6];
|
|
rt_kprintf("%s::Fatal Bus Error Inetrrupt Seen\n",__FUNCTION__);
|
|
|
|
memcpy(mac_addr0,dev->dev_addr,6);
|
|
synopGMAC_disable_dma_tx(gmacdev);
|
|
synopGMAC_disable_dma_rx(gmacdev);
|
|
|
|
synopGMAC_take_desc_ownership_tx(gmacdev);
|
|
synopGMAC_take_desc_ownership_rx(gmacdev);
|
|
|
|
synopGMAC_init_tx_rx_desc_queue(gmacdev);
|
|
|
|
synopGMAC_reset(gmacdev);
|
|
|
|
synopGMAC_set_mac_addr(gmacdev,GmacAddr0High,GmacAddr0Low, mac_addr0);
|
|
synopGMAC_dma_bus_mode_init(gmacdev,DmaFixedBurstEnable| DmaBurstLength8 | DmaDescriptorSkip2 );
|
|
synopGMAC_dma_control_init(gmacdev,DmaStoreAndForward);
|
|
synopGMAC_init_rx_desc_base(gmacdev);
|
|
synopGMAC_init_tx_desc_base(gmacdev);
|
|
synopGMAC_mac_init(gmacdev);
|
|
synopGMAC_enable_dma_rx(gmacdev);
|
|
synopGMAC_enable_dma_tx(gmacdev);
|
|
|
|
}
|
|
if(interrupt & synopGMACDmaRxNormal){
|
|
//DEBUG_MES("%s:: Rx Normal \n", __FUNCTION__);
|
|
//synop_handle_received_data(netdev);
|
|
eth_device_ready(ð_dev.parent);
|
|
}
|
|
if(interrupt & synopGMACDmaRxAbnormal){
|
|
//rt_kprintf("%s::Abnormal Rx Interrupt Seen\n",__FUNCTION__);
|
|
if(GMAC_Power_down == 0){
|
|
adapter->synopGMACNetStats.rx_over_errors++;
|
|
synopGMACWriteReg(gmacdev->DmaBase, DmaStatus ,0x80);
|
|
synopGMAC_resume_dma_rx(gmacdev);
|
|
}
|
|
}
|
|
if(interrupt & synopGMACDmaRxStopped){
|
|
rt_kprintf("%s::Receiver stopped seeing Rx interrupts\n",__FUNCTION__); //Receiver gone in to stopped state
|
|
}
|
|
|
|
if(interrupt & synopGMACDmaTxNormal){
|
|
DEBUG_MES("%s::Finished Normal Transmission \n",__FUNCTION__);
|
|
// synop_handle_transmit_over(netdev);
|
|
}
|
|
|
|
if(interrupt & synopGMACDmaTxAbnormal){
|
|
rt_kprintf("%s::Abnormal Tx Interrupt Seen\n",__FUNCTION__);
|
|
}
|
|
if(interrupt & synopGMACDmaTxStopped){
|
|
TR("%s::Transmitter stopped sending the packets\n",__FUNCTION__);
|
|
if(GMAC_Power_down == 0){ // If Mac is not in powerdown
|
|
synopGMAC_disable_dma_tx(gmacdev);
|
|
synopGMAC_take_desc_ownership_tx(gmacdev);
|
|
|
|
synopGMAC_enable_dma_tx(gmacdev);
|
|
// netif_wake_queue(netdev);
|
|
TR("%s::Transmission Resumed\n",__FUNCTION__);
|
|
}
|
|
}
|
|
/* Enable the interrrupt before returning from ISR*/
|
|
synopGMAC_enable_interrupt(gmacdev,DmaIntEnable);
|
|
|
|
return;
|
|
}
|
|
|
|
void rt_hw_eth_init(void)
|
|
{
|
|
u64 base_addr = Gmac_base;
|
|
struct synopGMACNetworkAdapter * synopGMACadapter;
|
|
static u8 mac_addr0[6] = DEFAULT_MAC_ADDRESS;
|
|
|
|
rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
|
|
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
|
|
|
|
|
|
memset(ð_dev, 0, sizeof(eth_dev));
|
|
synopGMACadapter = (struct synopGMACNetworkAdapter * )plat_alloc_memory(sizeof (struct synopGMACNetworkAdapter));
|
|
if(!synopGMACadapter){
|
|
rt_kprintf("Error in Memory Allocataion, Founction : %s \n", __FUNCTION__);
|
|
}
|
|
memset((char *)synopGMACadapter ,0, sizeof (struct synopGMACNetworkAdapter));
|
|
|
|
synopGMACadapter->synopGMACdev = NULL;
|
|
|
|
synopGMACadapter->synopGMACdev = (synopGMACdevice *) plat_alloc_memory(sizeof (synopGMACdevice));
|
|
if(!synopGMACadapter->synopGMACdev){
|
|
rt_kprintf("Error in Memory Allocataion, Founction : %s \n", __FUNCTION__);
|
|
}
|
|
memset((char *)synopGMACadapter->synopGMACdev ,0, sizeof (synopGMACdevice));
|
|
/*
|
|
* Attach the device to MAC struct This will configure all the required base addresses
|
|
* such as Mac base, configuration base, phy base address(out of 32 possible phys)
|
|
* */
|
|
synopGMAC_attach(synopGMACadapter->synopGMACdev,(regbase + MACBASE), regbase + DMABASE, DEFAULT_PHY_BASE, mac_addr0);
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|
|
|
init_phy(synopGMACadapter->synopGMACdev);
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|
synopGMAC_reset(synopGMACadapter->synopGMACdev);
|
|
|
|
/* MII setup */
|
|
synopGMACadapter->mii.phy_id_mask = 0x1F;
|
|
synopGMACadapter->mii.reg_num_mask = 0x1F;
|
|
synopGMACadapter->mii.dev = synopGMACadapter;
|
|
synopGMACadapter->mii.mdio_read = mdio_read;
|
|
synopGMACadapter->mii.mdio_write = mdio_write;
|
|
synopGMACadapter->mii.phy_id = synopGMACadapter->synopGMACdev->PhyBase;
|
|
synopGMACadapter->mii.supports_gmii = mii_check_gmii_support(&synopGMACadapter->mii);
|
|
|
|
eth_dev.iobase = base_addr;
|
|
eth_dev.name = "e0";
|
|
eth_dev.priv = synopGMACadapter;
|
|
eth_dev.dev_addr[0] = mac_addr0[0];
|
|
eth_dev.dev_addr[1] = mac_addr0[1];
|
|
eth_dev.dev_addr[2] = mac_addr0[2];
|
|
eth_dev.dev_addr[3] = mac_addr0[3];
|
|
eth_dev.dev_addr[4] = mac_addr0[4];
|
|
eth_dev.dev_addr[5] = mac_addr0[5];
|
|
|
|
eth_dev.parent.parent.type = RT_Device_Class_NetIf;
|
|
eth_dev.parent.parent.init = eth_init;
|
|
eth_dev.parent.parent.open = eth_open;
|
|
eth_dev.parent.parent.close = eth_close;
|
|
eth_dev.parent.parent.read = eth_read;
|
|
eth_dev.parent.parent.write = eth_write;
|
|
eth_dev.parent.parent.control = eth_control;
|
|
eth_dev.parent.parent.user_data = RT_NULL;
|
|
|
|
eth_dev.parent.eth_tx = rt_eth_tx;
|
|
eth_dev.parent.eth_rx = rt_eth_rx;
|
|
|
|
eth_device_init(&(eth_dev.parent), "e0");
|
|
}
|