622 lines
16 KiB
C
622 lines
16 KiB
C
/*
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* Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-07-01 lik first version
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*/
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#include "drv_gpio.h"
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#ifdef RT_USING_PIN
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#ifdef BSP_USING_GPIO
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//#define DRV_DEBUG
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#define LOG_TAG "drv.gpio"
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#include <drv_log.h>
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#define __SWM_PIN(index, gpio, pin_index) \
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{ \
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index, GPIO##gpio, PIN##pin_index, GPIO##gpio##_IRQn \
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}
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struct swm_pin_device
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{
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uint32_t index;
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GPIO_TypeDef *gpio;
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uint32_t pin;
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IRQn_Type irq;
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};
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static const struct swm_pin_device pin_obj[] =
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{
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__SWM_PIN(0, A, 0),
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__SWM_PIN(1, A, 1),
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__SWM_PIN(2, A, 2),
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__SWM_PIN(3, A, 3),
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__SWM_PIN(4, A, 4),
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__SWM_PIN(5, A, 5),
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__SWM_PIN(6, A, 6),
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__SWM_PIN(7, A, 7),
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__SWM_PIN(8, A, 8),
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__SWM_PIN(9, A, 9),
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__SWM_PIN(10, A, 10),
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__SWM_PIN(11, A, 11),
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__SWM_PIN(12, A, 12),
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__SWM_PIN(13, A, 13),
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__SWM_PIN(14, A, 14),
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__SWM_PIN(15, A, 15),
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__SWM_PIN(16, B, 0),
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__SWM_PIN(17, B, 1),
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__SWM_PIN(18, B, 2),
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__SWM_PIN(19, B, 3),
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__SWM_PIN(20, B, 4),
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__SWM_PIN(21, B, 5),
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__SWM_PIN(22, B, 6),
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__SWM_PIN(23, B, 7),
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__SWM_PIN(24, B, 8),
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__SWM_PIN(25, B, 9),
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__SWM_PIN(26, B, 10),
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__SWM_PIN(27, B, 11),
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__SWM_PIN(28, B, 12),
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__SWM_PIN(29, B, 13),
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__SWM_PIN(30, B, 14),
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__SWM_PIN(31, B, 15),
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__SWM_PIN(32, C, 0),
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__SWM_PIN(33, C, 1),
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__SWM_PIN(34, C, 2),
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__SWM_PIN(35, C, 3),
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__SWM_PIN(36, C, 4),
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__SWM_PIN(37, C, 5),
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__SWM_PIN(38, C, 6),
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__SWM_PIN(39, C, 7),
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__SWM_PIN(40, C, 8),
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__SWM_PIN(41, C, 9),
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__SWM_PIN(42, C, 10),
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__SWM_PIN(43, C, 11),
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__SWM_PIN(44, C, 12),
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__SWM_PIN(45, C, 13),
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__SWM_PIN(46, C, 14),
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__SWM_PIN(47, C, 15),
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__SWM_PIN(48, D, 0),
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__SWM_PIN(49, D, 1),
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__SWM_PIN(50, D, 2),
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__SWM_PIN(51, D, 3),
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__SWM_PIN(52, D, 4),
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__SWM_PIN(53, D, 5),
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__SWM_PIN(54, D, 6),
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__SWM_PIN(55, D, 7),
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__SWM_PIN(56, D, 8),
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__SWM_PIN(57, D, 9),
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__SWM_PIN(58, D, 10),
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__SWM_PIN(59, D, 11),
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__SWM_PIN(60, D, 12),
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__SWM_PIN(61, D, 13),
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__SWM_PIN(62, D, 14),
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__SWM_PIN(63, D, 15),
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__SWM_PIN(64, E, 0),
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__SWM_PIN(65, E, 1),
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__SWM_PIN(66, E, 2),
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__SWM_PIN(67, E, 3),
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__SWM_PIN(68, E, 4),
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__SWM_PIN(69, E, 5),
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__SWM_PIN(70, E, 6),
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__SWM_PIN(71, E, 7),
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__SWM_PIN(72, E, 8),
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__SWM_PIN(73, E, 9),
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__SWM_PIN(74, E, 10),
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__SWM_PIN(75, E, 11),
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__SWM_PIN(76, E, 12),
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__SWM_PIN(77, E, 13),
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__SWM_PIN(78, E, 14),
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__SWM_PIN(79, E, 15),
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__SWM_PIN(80, M, 0),
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__SWM_PIN(81, M, 1),
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__SWM_PIN(82, M, 2),
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__SWM_PIN(83, M, 3),
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__SWM_PIN(84, M, 4),
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__SWM_PIN(85, M, 5),
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__SWM_PIN(86, M, 6),
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__SWM_PIN(87, M, 7),
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__SWM_PIN(88, M, 8),
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__SWM_PIN(89, M, 9),
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__SWM_PIN(90, M, 10),
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__SWM_PIN(91, M, 11),
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__SWM_PIN(92, M, 12),
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__SWM_PIN(93, M, 13),
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__SWM_PIN(94, M, 14),
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__SWM_PIN(95, M, 15),
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__SWM_PIN(96, N, 0),
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__SWM_PIN(97, N, 1),
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__SWM_PIN(98, N, 2),
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__SWM_PIN(99, N, 3),
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__SWM_PIN(100, N, 4),
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__SWM_PIN(101, N, 5),
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__SWM_PIN(102, N, 6),
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__SWM_PIN(103, N, 7),
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__SWM_PIN(104, N, 8),
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__SWM_PIN(105, N, 9),
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__SWM_PIN(106, N, 10),
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__SWM_PIN(107, N, 11),
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__SWM_PIN(108, N, 12),
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__SWM_PIN(109, N, 13),
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__SWM_PIN(110, N, 14),
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__SWM_PIN(111, N, 15)};
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static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{0, 0, RT_NULL, RT_NULL},
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{1, 0, RT_NULL, RT_NULL},
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{2, 0, RT_NULL, RT_NULL},
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{3, 0, RT_NULL, RT_NULL},
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{4, 0, RT_NULL, RT_NULL},
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{5, 0, RT_NULL, RT_NULL},
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{6, 0, RT_NULL, RT_NULL},
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{7, 0, RT_NULL, RT_NULL},
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{8, 0, RT_NULL, RT_NULL},
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{9, 0, RT_NULL, RT_NULL},
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{10, 0, RT_NULL, RT_NULL},
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{11, 0, RT_NULL, RT_NULL},
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{12, 0, RT_NULL, RT_NULL},
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{13, 0, RT_NULL, RT_NULL},
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{14, 0, RT_NULL, RT_NULL},
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{15, 0, RT_NULL, RT_NULL},
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{16, 0, RT_NULL, RT_NULL},
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{17, 0, RT_NULL, RT_NULL},
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{18, 0, RT_NULL, RT_NULL},
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{19, 0, RT_NULL, RT_NULL},
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{20, 0, RT_NULL, RT_NULL},
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{21, 0, RT_NULL, RT_NULL},
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{22, 0, RT_NULL, RT_NULL},
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{23, 0, RT_NULL, RT_NULL},
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{24, 0, RT_NULL, RT_NULL},
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{25, 0, RT_NULL, RT_NULL},
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{26, 0, RT_NULL, RT_NULL},
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{27, 0, RT_NULL, RT_NULL},
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{28, 0, RT_NULL, RT_NULL},
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{29, 0, RT_NULL, RT_NULL},
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{30, 0, RT_NULL, RT_NULL},
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{31, 0, RT_NULL, RT_NULL},
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{32, 0, RT_NULL, RT_NULL},
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{33, 0, RT_NULL, RT_NULL},
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{34, 0, RT_NULL, RT_NULL},
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{35, 0, RT_NULL, RT_NULL},
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{36, 0, RT_NULL, RT_NULL},
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{37, 0, RT_NULL, RT_NULL},
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{38, 0, RT_NULL, RT_NULL},
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{39, 0, RT_NULL, RT_NULL},
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{40, 0, RT_NULL, RT_NULL},
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{41, 0, RT_NULL, RT_NULL},
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{42, 0, RT_NULL, RT_NULL},
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{43, 0, RT_NULL, RT_NULL},
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{44, 0, RT_NULL, RT_NULL},
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{45, 0, RT_NULL, RT_NULL},
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{46, 0, RT_NULL, RT_NULL},
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{47, 0, RT_NULL, RT_NULL},
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{48, 0, RT_NULL, RT_NULL},
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{49, 0, RT_NULL, RT_NULL},
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{50, 0, RT_NULL, RT_NULL},
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{51, 0, RT_NULL, RT_NULL},
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{52, 0, RT_NULL, RT_NULL},
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{53, 0, RT_NULL, RT_NULL},
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{54, 0, RT_NULL, RT_NULL},
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{55, 0, RT_NULL, RT_NULL},
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{56, 0, RT_NULL, RT_NULL},
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{57, 0, RT_NULL, RT_NULL},
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{58, 0, RT_NULL, RT_NULL},
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{59, 0, RT_NULL, RT_NULL},
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{60, 0, RT_NULL, RT_NULL},
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{61, 0, RT_NULL, RT_NULL},
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{62, 0, RT_NULL, RT_NULL},
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{63, 0, RT_NULL, RT_NULL},
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{64, 0, RT_NULL, RT_NULL},
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{65, 0, RT_NULL, RT_NULL},
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{66, 0, RT_NULL, RT_NULL},
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{67, 0, RT_NULL, RT_NULL},
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{68, 0, RT_NULL, RT_NULL},
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{69, 0, RT_NULL, RT_NULL},
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{70, 0, RT_NULL, RT_NULL},
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{71, 0, RT_NULL, RT_NULL},
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{72, 0, RT_NULL, RT_NULL},
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{73, 0, RT_NULL, RT_NULL},
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{74, 0, RT_NULL, RT_NULL},
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{75, 0, RT_NULL, RT_NULL},
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{76, 0, RT_NULL, RT_NULL},
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{77, 0, RT_NULL, RT_NULL},
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{78, 0, RT_NULL, RT_NULL},
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{79, 0, RT_NULL, RT_NULL},
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{80, 0, RT_NULL, RT_NULL},
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{81, 0, RT_NULL, RT_NULL},
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{82, 0, RT_NULL, RT_NULL},
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{83, 0, RT_NULL, RT_NULL},
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{84, 0, RT_NULL, RT_NULL},
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{85, 0, RT_NULL, RT_NULL},
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{86, 0, RT_NULL, RT_NULL},
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{87, 0, RT_NULL, RT_NULL},
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{88, 0, RT_NULL, RT_NULL},
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{89, 0, RT_NULL, RT_NULL},
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{90, 0, RT_NULL, RT_NULL},
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{91, 0, RT_NULL, RT_NULL},
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{92, 0, RT_NULL, RT_NULL},
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{93, 0, RT_NULL, RT_NULL},
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{94, 0, RT_NULL, RT_NULL},
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{95, 0, RT_NULL, RT_NULL},
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{96, 0, RT_NULL, RT_NULL},
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{97, 0, RT_NULL, RT_NULL},
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{98, 0, RT_NULL, RT_NULL},
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{99, 0, RT_NULL, RT_NULL},
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{100, 0, RT_NULL, RT_NULL},
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{101, 0, RT_NULL, RT_NULL},
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{102, 0, RT_NULL, RT_NULL},
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{103, 0, RT_NULL, RT_NULL},
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{104, 0, RT_NULL, RT_NULL},
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{105, 0, RT_NULL, RT_NULL},
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{106, 0, RT_NULL, RT_NULL},
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{107, 0, RT_NULL, RT_NULL},
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{108, 0, RT_NULL, RT_NULL},
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{109, 0, RT_NULL, RT_NULL},
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{110, 0, RT_NULL, RT_NULL},
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{111, 0, RT_NULL, RT_NULL}};
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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static const struct swm_pin_device *_pin2struct(uint8_t pin)
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{
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const struct swm_pin_device *gpio_obj;
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if (pin < ITEM_NUM(pin_obj))
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{
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gpio_obj = &pin_obj[pin];
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}
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else
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{
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gpio_obj = RT_NULL;
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}
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return gpio_obj;
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}
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static void swm_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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const struct swm_pin_device *gpio_obj;
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int dir = 0;
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int pull_up = 0;
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int pull_down = 0;
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int open_drain = 0;
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gpio_obj = _pin2struct(pin);
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if (gpio_obj == RT_NULL)
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{
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return;
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}
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/* Configure GPIO_InitStructure */
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switch (mode)
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{
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case PIN_MODE_OUTPUT:
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/* output setting */
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dir = 1;
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break;
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case PIN_MODE_INPUT:
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/* input setting: not pull. */
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dir = 0;
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break;
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case PIN_MODE_INPUT_PULLUP:
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/* input setting: pull up. */
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dir = 0;
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pull_up = 1;
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break;
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case PIN_MODE_INPUT_PULLDOWN:
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/* input setting: pull down. */
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dir = 0;
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pull_down = 1;
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break;
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case PIN_MODE_OUTPUT_OD:
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/* output setting: od. */
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dir = 1;
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open_drain = 1;
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break;
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}
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GPIO_Init(gpio_obj->gpio, gpio_obj->pin, dir, pull_up, pull_down, open_drain);
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}
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static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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const struct swm_pin_device *gpio_obj;
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gpio_obj = _pin2struct(pin);
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if (gpio_obj == RT_NULL)
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{
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return;
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}
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if (value)
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{
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GPIO_AtomicSetBit(gpio_obj->gpio, gpio_obj->pin);
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}
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else
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{
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GPIO_AtomicClrBit(gpio_obj->gpio, gpio_obj->pin);
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}
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}
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static int swm_pin_read(rt_device_t dev, rt_base_t pin)
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{
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const struct swm_pin_device *gpio_obj;
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gpio_obj = _pin2struct(pin);
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if (gpio_obj == RT_NULL)
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{
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return PIN_LOW;
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}
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return (int)GPIO_GetBit(gpio_obj->gpio, gpio_obj->pin);
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}
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static rt_err_t swm_pin_attach_irq(struct rt_device *device,
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rt_int32_t pin,
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rt_uint32_t mode,
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void (*hdr)(void *args),
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void *args)
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{
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rt_base_t level;
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[pin].pin == pin &&
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pin_irq_hdr_tab[pin].mode == mode &&
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pin_irq_hdr_tab[pin].hdr == hdr &&
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pin_irq_hdr_tab[pin].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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pin_irq_hdr_tab[pin].pin = pin;
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pin_irq_hdr_tab[pin].mode = mode;
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pin_irq_hdr_tab[pin].hdr = hdr;
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pin_irq_hdr_tab[pin].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t swm_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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{
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rt_base_t level;
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level = rt_hw_interrupt_disable();
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pin_irq_hdr_tab[pin].mode = 0;
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pin_irq_hdr_tab[pin].hdr = RT_NULL;
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pin_irq_hdr_tab[pin].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t swm_pin_irq_enable(struct rt_device *device,
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rt_base_t pin,
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rt_uint32_t enabled)
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{
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const struct swm_pin_device *gpio_obj;
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rt_base_t level = 0;
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gpio_obj = _pin2struct(pin);
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if (gpio_obj == RT_NULL)
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{
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return -RT_ENOSYS;
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}
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if (enabled == PIN_IRQ_ENABLE)
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{
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switch (pin_irq_hdr_tab[pin].mode)
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{
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case PIN_IRQ_MODE_RISING:
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GPIO_Init(gpio_obj->gpio, gpio_obj->pin, 0, 0, 1, 0);
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EXTI_Init(gpio_obj->gpio, gpio_obj->pin, EXTI_RISE_EDGE);
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break;
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case PIN_IRQ_MODE_FALLING:
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GPIO_Init(gpio_obj->gpio, gpio_obj->pin, 0, 1, 0, 0);
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EXTI_Init(gpio_obj->gpio, gpio_obj->pin, EXTI_FALL_EDGE);
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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GPIO_Init(gpio_obj->gpio, gpio_obj->pin, 0, 1, 1, 0);
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EXTI_Init(gpio_obj->gpio, gpio_obj->pin, EXTI_BOTH_EDGE);
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break;
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case PIN_IRQ_MODE_HIGH_LEVEL:
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GPIO_Init(gpio_obj->gpio, gpio_obj->pin, 0, 0, 1, 0);
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EXTI_Init(gpio_obj->gpio, gpio_obj->pin, EXTI_HIGH_LEVEL);
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break;
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case PIN_IRQ_MODE_LOW_LEVEL:
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GPIO_Init(gpio_obj->gpio, gpio_obj->pin, 0, 1, 0, 0);
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EXTI_Init(gpio_obj->gpio, gpio_obj->pin, EXTI_LOW_LEVEL);
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break;
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default:
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return -RT_EINVAL;
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}
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level = rt_hw_interrupt_disable();
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NVIC_EnableIRQ(gpio_obj->irq);
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EXTI_Open(gpio_obj->gpio, gpio_obj->pin);
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rt_hw_interrupt_enable(level);
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}
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else if (enabled == PIN_IRQ_DISABLE)
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{
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level = rt_hw_interrupt_disable();
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// NVIC_DisableIRQ(gpio_obj->irq);
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EXTI_Close(gpio_obj->gpio, gpio_obj->pin);
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rt_hw_interrupt_enable(level);
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}
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else
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{
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return -RT_ENOSYS;
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}
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return RT_EOK;
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}
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static rt_base_t swm_pin_get(const char *name)
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{
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rt_base_t pin = 0;
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int pin_num = 0;
|
|
int i, name_len;
|
|
|
|
name_len = rt_strlen(name);
|
|
|
|
if ((name_len < 4) || (name_len >= 6))
|
|
{
|
|
return -RT_EINVAL;
|
|
}
|
|
if ((name[0] != 'P') || (name[2] != '.'))
|
|
{
|
|
return -RT_EINVAL;
|
|
}
|
|
|
|
switch(name[1])
|
|
{
|
|
case 'A':
|
|
pin = 0;
|
|
break;
|
|
case 'B':
|
|
pin = 16;
|
|
break;
|
|
case 'C':
|
|
pin = 32;
|
|
break;
|
|
case 'D':
|
|
pin = 48;
|
|
break;
|
|
case 'E':
|
|
pin = 64;
|
|
break;
|
|
case 'M':
|
|
pin = 80;
|
|
break;
|
|
case 'N':
|
|
pin = 96;
|
|
break;
|
|
default:
|
|
return -RT_EINVAL;
|
|
}
|
|
|
|
for (i = 3; i < name_len; i++)
|
|
{
|
|
pin_num *= 10;
|
|
pin_num += name[i] - '0';
|
|
}
|
|
if(pin_num < 16)
|
|
{
|
|
pin += pin_num;
|
|
}
|
|
else
|
|
{
|
|
return -RT_EINVAL;
|
|
}
|
|
|
|
return pin;
|
|
}
|
|
|
|
static const struct rt_pin_ops swm_pin_ops =
|
|
{
|
|
.pin_mode = swm_pin_mode,
|
|
.pin_write = swm_pin_write,
|
|
.pin_read = swm_pin_read,
|
|
.pin_attach_irq = swm_pin_attach_irq,
|
|
.pin_detach_irq = swm_pin_detach_irq,
|
|
.pin_irq_enable = swm_pin_irq_enable,
|
|
.pin_get = swm_pin_get};
|
|
|
|
static void swm_pin_isr(GPIO_TypeDef *GPIOx)
|
|
{
|
|
static int gpio[16];
|
|
int index = 0;
|
|
static int init = 0;
|
|
const struct swm_pin_device *gpio_obj;
|
|
|
|
if (init == 0)
|
|
{
|
|
init = 1;
|
|
for (gpio_obj = &pin_obj[0];
|
|
gpio_obj->index < ITEM_NUM(pin_obj);
|
|
gpio_obj++)
|
|
{
|
|
if (gpio_obj->gpio == GPIOx)
|
|
{
|
|
gpio[index] = gpio_obj->index;
|
|
index++;
|
|
RT_ASSERT(index <= 16)
|
|
}
|
|
}
|
|
}
|
|
for (index = 0; index < 16; index++)
|
|
{
|
|
gpio_obj = _pin2struct(gpio[index]);
|
|
if (EXTI_State(gpio_obj->gpio, gpio_obj->pin))
|
|
{
|
|
EXTI_Clear(gpio_obj->gpio, gpio_obj->pin);
|
|
if (pin_irq_hdr_tab[gpio_obj->index].hdr)
|
|
{
|
|
pin_irq_hdr_tab[gpio_obj->index].hdr(pin_irq_hdr_tab[gpio_obj->index].args);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void GPIOA_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
swm_pin_isr(GPIOA);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void GPIOB_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
swm_pin_isr(GPIOB);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void GPIOC_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
swm_pin_isr(GPIOC);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void GPIOD_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
swm_pin_isr(GPIOD);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void GPIOE_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
swm_pin_isr(GPIOE);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void GPIOM_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
swm_pin_isr(GPIOM);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void GPION_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
swm_pin_isr(GPION);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
int swm_pin_init(void)
|
|
{
|
|
return rt_device_pin_register("pin", &swm_pin_ops, RT_NULL);
|
|
}
|
|
|
|
#endif /* BSP_USING_GPIO */
|
|
#endif /* RT_USING_PIN */
|