358 lines
13 KiB
C
358 lines
13 KiB
C
/* generated HAL source file - do not edit */
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#include "hal_data.h"
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/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */
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#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC
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#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC
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#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC
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#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC
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gpt_instance_ctrl_t g_timer2_ctrl;
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#if 0
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const gpt_extended_pwm_cfg_t g_timer2_pwm_extend =
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{
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.trough_ipl = (BSP_IRQ_DISABLED),
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#if defined(VECTOR_NUMBER_GPT2_COUNTER_UNDERFLOW)
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.trough_irq = VECTOR_NUMBER_GPT2_COUNTER_UNDERFLOW,
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#else
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.trough_irq = FSP_INVALID_VECTOR,
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#endif
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.poeg_link = GPT_POEG_LINK_POEG0,
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.output_disable = GPT_OUTPUT_DISABLE_NONE,
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.adc_trigger = GPT_ADC_TRIGGER_NONE,
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.dead_time_count_up = 0,
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.dead_time_count_down = 0,
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.adc_a_compare_match = 0,
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.adc_b_compare_match = 0,
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.interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE,
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.interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0,
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.interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE,
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.gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED,
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.gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED,
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};
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#endif
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const gpt_extended_cfg_t g_timer2_extend =
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{
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.gtioca = { .output_enabled = false,
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.stop_level = GPT_PIN_LEVEL_LOW
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},
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.gtiocb = { .output_enabled = true,
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.stop_level = GPT_PIN_LEVEL_LOW
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},
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.start_source = (gpt_source_t) ( GPT_SOURCE_NONE),
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.stop_source = (gpt_source_t) ( GPT_SOURCE_NONE),
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.clear_source = (gpt_source_t) ( GPT_SOURCE_NONE),
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.count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE),
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.count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE),
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.capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE),
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.capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE),
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.capture_a_ipl = (BSP_IRQ_DISABLED),
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.capture_b_ipl = (BSP_IRQ_DISABLED),
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#if defined(VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_A)
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.capture_a_irq = VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_A,
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#else
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.capture_a_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_B)
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.capture_b_irq = VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_B,
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#else
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.capture_b_irq = FSP_INVALID_VECTOR,
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#endif
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.capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE,
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.capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE,
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#if 0
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.p_pwm_cfg = &g_timer2_pwm_extend,
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#else
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.p_pwm_cfg = NULL,
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#endif
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#if 0
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.gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U),
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.gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW,
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.gtior_setting.gtior_b.oahld = 0U,
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.gtior_setting.gtior_b.oae = (uint32_t) false,
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.gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED,
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.gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U),
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.gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U),
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.gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U),
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.gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW,
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.gtior_setting.gtior_b.obhld = 0U,
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.gtior_setting.gtior_b.obe = (uint32_t) true,
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.gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED,
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.gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U),
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.gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U),
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#else
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.gtior_setting.gtior = 0U,
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#endif
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};
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const timer_cfg_t g_timer2_cfg =
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{
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.mode = TIMER_MODE_PWM,
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/* Actual period: 35.791394133333334 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x100000000, .duty_cycle_counts = 0x80000000, .source_div = (timer_source_div_t)0,
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.channel = 2,
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.p_callback = NULL,
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/** If NULL then do not add & */
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#if defined(NULL)
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.p_context = NULL,
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#else
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.p_context = &NULL,
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#endif
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.p_extend = &g_timer2_extend,
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.cycle_end_ipl = (BSP_IRQ_DISABLED),
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#if defined(VECTOR_NUMBER_GPT2_COUNTER_OVERFLOW)
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.cycle_end_irq = VECTOR_NUMBER_GPT2_COUNTER_OVERFLOW,
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#else
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.cycle_end_irq = FSP_INVALID_VECTOR,
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#endif
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};
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/* Instance structure to use this module. */
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const timer_instance_t g_timer2 =
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{
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.p_ctrl = &g_timer2_ctrl,
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.p_cfg = &g_timer2_cfg,
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.p_api = &g_timer_on_gpt
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};
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sci_uart_instance_ctrl_t g_uart4_ctrl;
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baud_setting_t g_uart4_baud_setting =
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{
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/* Baud rate calculated with 0.160% error. */ .abcse = 0, .abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t) 256, .brme = false
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};
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/** UART extended configuration for UARTonSCI HAL driver */
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const sci_uart_extended_cfg_t g_uart4_cfg_extend =
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{
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.clock = SCI_UART_CLOCK_INT,
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.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
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.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
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.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
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.p_baud_setting = &g_uart4_baud_setting,
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.flow_control = SCI_UART_FLOW_CONTROL_RTS,
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#if 0xFF != 0xFF
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.flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
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#else
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.flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX,
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#endif
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};
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/** UART interface configuration */
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const uart_cfg_t g_uart4_cfg =
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{
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.channel = 4,
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.data_bits = UART_DATA_BITS_8,
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.parity = UART_PARITY_OFF,
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.stop_bits = UART_STOP_BITS_1,
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.p_callback = user_uart4_callback,
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.p_context = NULL,
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.p_extend = &g_uart4_cfg_extend,
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#define RA_NOT_DEFINED (1)
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#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
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.p_transfer_tx = NULL,
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#else
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.p_transfer_tx = &RA_NOT_DEFINED,
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#endif
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#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
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.p_transfer_rx = NULL,
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#else
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.p_transfer_rx = &RA_NOT_DEFINED,
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#endif
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#undef RA_NOT_DEFINED
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.rxi_ipl = (12),
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.txi_ipl = (12),
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.tei_ipl = (12),
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.eri_ipl = (12),
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#if defined(VECTOR_NUMBER_SCI4_RXI)
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.rxi_irq = VECTOR_NUMBER_SCI4_RXI,
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#else
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.rxi_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SCI4_TXI)
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.txi_irq = VECTOR_NUMBER_SCI4_TXI,
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#else
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.txi_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SCI4_TEI)
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.tei_irq = VECTOR_NUMBER_SCI4_TEI,
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#else
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.tei_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SCI4_ERI)
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.eri_irq = VECTOR_NUMBER_SCI4_ERI,
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#else
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.eri_irq = FSP_INVALID_VECTOR,
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#endif
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};
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/* Instance structure to use this module. */
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const uart_instance_t g_uart4 =
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{
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.p_ctrl = &g_uart4_ctrl,
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.p_cfg = &g_uart4_cfg,
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.p_api = &g_uart_on_sci
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};
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adc_instance_ctrl_t g_adc0_ctrl;
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const adc_extended_cfg_t g_adc0_cfg_extend =
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{
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.add_average_count = ADC_ADD_OFF,
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.clearing = ADC_CLEAR_AFTER_READ_ON,
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.trigger_group_b = ADC_TRIGGER_SYNC_ELC,
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.double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED,
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.adc_vref_control = ADC_VREF_CONTROL_VREFH,
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.enable_adbuf = 0,
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#if defined(VECTOR_NUMBER_ADC0_WINDOW_A)
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.window_a_irq = VECTOR_NUMBER_ADC0_WINDOW_A,
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#else
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.window_a_irq = FSP_INVALID_VECTOR,
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#endif
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.window_a_ipl = (BSP_IRQ_DISABLED),
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#if defined(VECTOR_NUMBER_ADC0_WINDOW_B)
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.window_b_irq = VECTOR_NUMBER_ADC0_WINDOW_B,
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#else
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.window_b_irq = FSP_INVALID_VECTOR,
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#endif
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.window_b_ipl = (BSP_IRQ_DISABLED),
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};
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const adc_cfg_t g_adc0_cfg =
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{
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.unit = 0,
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.mode = ADC_MODE_CONTINUOUS_SCAN,
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.resolution = ADC_RESOLUTION_12_BIT,
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.alignment = (adc_alignment_t) ADC_ALIGNMENT_RIGHT,
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.trigger = ADC_TRIGGER_SOFTWARE,
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.p_callback = NULL,
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/** If NULL then do not add & */
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#if defined(NULL)
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.p_context = NULL,
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#else
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.p_context = &NULL,
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#endif
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.p_extend = &g_adc0_cfg_extend,
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#if defined(VECTOR_NUMBER_ADC0_SCAN_END)
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.scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END,
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#else
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.scan_end_irq = FSP_INVALID_VECTOR,
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#endif
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.scan_end_ipl = (BSP_IRQ_DISABLED),
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#if defined(VECTOR_NUMBER_ADC0_SCAN_END_B)
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.scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B,
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#else
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.scan_end_b_irq = FSP_INVALID_VECTOR,
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#endif
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.scan_end_b_ipl = (BSP_IRQ_DISABLED),
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};
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#if ((0) | (0))
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const adc_window_cfg_t g_adc0_window_cfg =
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{
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.compare_mask = 0,
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.compare_mode_mask = 0,
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.compare_cfg = (0) | (0) | (0) | (ADC_COMPARE_CFG_EVENT_OUTPUT_OR),
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.compare_ref_low = 0,
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.compare_ref_high = 0,
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.compare_b_channel = (ADC_WINDOW_B_CHANNEL_0),
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.compare_b_mode = (ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE),
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.compare_b_ref_low = 0,
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.compare_b_ref_high = 0,
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};
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#endif
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const adc_channel_cfg_t g_adc0_channel_cfg =
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{
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.scan_mask = ADC_MASK_CHANNEL_0 | ADC_MASK_CHANNEL_1 | ADC_MASK_CHANNEL_2 | ADC_MASK_CHANNEL_3 | ADC_MASK_CHANNEL_5 | ADC_MASK_CHANNEL_7 | ADC_MASK_CHANNEL_20 | 0,
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.scan_mask_group_b = 0,
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.priority_group_a = ADC_GROUP_A_PRIORITY_OFF,
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.add_mask = 0,
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.sample_hold_mask = 0,
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.sample_hold_states = 24,
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#if ((0) | (0))
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.p_window_cfg = (adc_window_cfg_t *) &g_adc0_window_cfg,
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#else
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.p_window_cfg = NULL,
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#endif
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};
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/* Instance structure to use this module. */
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const adc_instance_t g_adc0 =
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{
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.p_ctrl = &g_adc0_ctrl,
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.p_cfg = &g_adc0_cfg,
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.p_channel_cfg = &g_adc0_channel_cfg,
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.p_api = &g_adc_on_adc
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};
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sci_uart_instance_ctrl_t g_uart9_ctrl;
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baud_setting_t g_uart9_baud_setting =
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{
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/* Baud rate calculated with 0.160% error. */ .abcse = 0, .abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t) 256, .brme = false
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};
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/** UART extended configuration for UARTonSCI HAL driver */
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const sci_uart_extended_cfg_t g_uart9_cfg_extend =
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{
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.clock = SCI_UART_CLOCK_INT,
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.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
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.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
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.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
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.p_baud_setting = &g_uart9_baud_setting,
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.flow_control = SCI_UART_FLOW_CONTROL_RTS,
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#if 0xFF != 0xFF
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.flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
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#else
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.flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX,
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#endif
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};
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/** UART interface configuration */
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const uart_cfg_t g_uart9_cfg =
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{
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.channel = 9,
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.data_bits = UART_DATA_BITS_8,
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.parity = UART_PARITY_OFF,
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.stop_bits = UART_STOP_BITS_1,
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.p_callback = user_uart9_callback,
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.p_context = NULL,
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.p_extend = &g_uart9_cfg_extend,
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#define RA_NOT_DEFINED (1)
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#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
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.p_transfer_tx = NULL,
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#else
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.p_transfer_tx = &RA_NOT_DEFINED,
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#endif
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#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
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.p_transfer_rx = NULL,
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#else
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.p_transfer_rx = &RA_NOT_DEFINED,
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#endif
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#undef RA_NOT_DEFINED
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.rxi_ipl = (12),
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.txi_ipl = (12),
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.tei_ipl = (12),
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.eri_ipl = (12),
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#if defined(VECTOR_NUMBER_SCI9_RXI)
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.rxi_irq = VECTOR_NUMBER_SCI9_RXI,
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#else
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.rxi_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SCI9_TXI)
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.txi_irq = VECTOR_NUMBER_SCI9_TXI,
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#else
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.txi_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SCI9_TEI)
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.tei_irq = VECTOR_NUMBER_SCI9_TEI,
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#else
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.tei_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SCI9_ERI)
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.eri_irq = VECTOR_NUMBER_SCI9_ERI,
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#else
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.eri_irq = FSP_INVALID_VECTOR,
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#endif
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};
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/* Instance structure to use this module. */
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const uart_instance_t g_uart9 =
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{
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.p_ctrl = &g_uart9_ctrl,
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.p_cfg = &g_uart9_cfg,
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.p_api = &g_uart_on_sci
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};
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void g_hal_init(void) {
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g_common_init();
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}
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